Variable length data processing apparatus for consecutively processing variable-length data responsive to one instruction

• US 4,975,835 A
• Filed: 10/14/1988
• Issued: 12/04/1990
• Est. Priority Date: 10/30/1987
• Status: Expired due to Fees

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Hidaka, Norihiro, Sato, Tetsuya, Ito, Shin, Kimura, Makoto
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US07/258,153
• Time in Patent Office: 781 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/225
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

Data divided by delimiters representing the boundaries of the data is stored in a data memory. Instructions each including designation of a delimiter are stored in an instruction register. A control circuit decodes an instruction output from the instruction register, and repeats processing of the data read out from the data memory in accordance with the decoded instruction every time the data is read out therefrom. A delimiter detector outputs a coincidence signal when it detects that a delimiter which coincides with the delimiter in the instruction is present in the data read out from the data memory. When this coincidence signal is input to the control circuit, the control circuit ends the processing which has been performed in accordance with the instruction.

Claims

1. An apparatus for consecutively processing variable-length data by one instruction, comprising:

data storage means for storing a plurality of variable length data each divided by a delimiter;

instruction storage means for storing a plurality of instructions which include designation of a delimiter;

means for reading out an instruction from said instruction storage means;

address generating means coupled to said data storage means, for consecutively outputting addresses to said data storage means;

data processing means coupled to said instruction storage means and to said data storage means, for decoding one of the instructions read out from said instruction storage means which designates a delimiter, and for consecutively processing variable-length data in accordance with said one decoded instruction, the variable-length data being consecutively read out from said data storage means by using the addresses output from said address generating means;

delimiter detecting means coupled to said data storage means and to said instruction storage means, for outputting a coincidence signal upon detecting that a delimiter from said data storage means which coincides with a delimiter designated by said one decoded instruction is present in said consecutively read out data; and

control means coupled to said delimiter detecting means, and responsive to the coincidence signal from said delimiter detecting means, for ending said consecutive processing of variable-length data performed in accordance with said one decoded instruction.

2. The apparatus according to claim 1, wherein the designation of a delimiter includes at least one of delimiter data and data corresponding to a delimiter.

3. The apparatus according to claim 2, wherein the delimiter data include a delimiter per se.

4. The apparatus according to claim 1, wherein:

the delimiter in said data storage means includes a plurality of codes to which weighted priorities for processing are assigned; and

said delimiter detecting means includes means for outputting the coincidence signal to said control means upon detecting that a delimiter read out from said data storage means has a higher priority than the delimiter designated by said one decoded instruction.

5. An apparatus for consecutively processing variable length data by one instruction, comprising:

data storage means for storing a plurality of variable length data each divided by a delimiter;

instruction storage means for storing a plurality of instructions which include designation of a delimiter;

means for reading out an instruction from said instruction storage means;

address generating means coupled to said data storage means, for consecutively outputting addresses to said data storage means;

data processing means coupled to said instruction storage means and to said data storage means, for decoding one of the instructions read out from said instruction storage means which designates a delimiter, and for consecutively processing variable-length data in accordance with said one decoded instruction, the variable-length data being consecutively read out from said data storage means by using the addresses output from said address generating means;

delimiter detecting means coupled to said data storage means and to said instruction storage means, for outputting a coincidence signal upon detecting that a delimiter from said data storage means which coincides with a delimiter designated by said one decoded instruction is present in said consecutively read out data;

counting means coupled to said delimiter detecting means, for counting coincidence signals output from said delimiter detecting means; and

control means coupled to said counting means, for ending said consecutive processing of variable-length data performed in accordance with said one instruction in response to a count value of said counting means reaching a specific value.

6. The apparatus according to claim 5, wherein:

the delimiter in said data storage means includes a plurality of codes to which weighted priorities for processing are assigned;

said delimiter detecting means includes means for outputting a specific detection signal to said control means upon detecting that a delimiter read out from said data storage means has a higher priority than the delimiter designated by said one decoded instruction; and

said control means includes means for ending said consecutive processing of said variable-length data which is performed in accordance with the one decoded instruction when said specific detection signal is input to said control means.

7. The apparatus according to claim 5, wherein the designation of a delimiter includes at least one of delimiter data and data corresponding to a delimiter.

8. The apparatus according to claim 7, wherein the delimiter data includes a delimiter per se.

9. An apparatus for consecutively processing variable length data by one instruction, comprising:

data storage means for storing a plurality of variable length data each divided by a delimiter;

instruction storage means for storing a plurality of instructions which include designation of a delimiter;

means for reading out an instruction from said instruction storage means;

address generating means coupled to said data storage means, for consecutively outputting addresses to said data storage means;

data processing means coupled to said instruction storage means and to said data storage means, for decoding one of the instructions read out from said instruction storage means which designates a delimiter, and for consecutively processing variable-length data in accordance with said one decoded instruction, the variable-length data being consecutively read out from said data storage means by using the addresses output from said address generating means;

delimiter detecting means coupled to said data storage means and to said instruction storage means, for outputting a coincidence signal upon detecting that a delimiter from said data storage means which coincides with a delimiter designated by said one decoded instruction is present in said consecutively read out data; and

counting means coupled to said data processing means, for counting a number of data items read out from said data storage means;

control means coupled to said delimiter detecting means and to said counting means, for ending said consecutive processing of variable data performed in accordance with said one decoded instruction in response to the coincidence signal from said delimiter detecting means or a count value of said counting means reaching a specific value.

10. The apparatus according to claim 9, wherein:

the delimiter in said data storage means includes a plurality of codes to which weighted priorities for processing are assigned; and

said delimiter detecting means includes means for outputting the coincidence signal to said control means upon detecting that a delimiter read out from said data storage means has a higher priority than the delimiter designated by said one decoded instruction.

11. The apparatus according to claim 9, wherein the designation of a delimiter includes at least one of delimiter data and data corresponding to a delimiter.

12. The apparatus according to claim 11, wherein the delimiter data includes a delimiter per se.

13. A processor for consecutively processing variable length data in accordance with one instruction, the length of the variable-length data being defined by at least one delimiter, comprising:

instruction storage means for storing one instruction including an operation portion designating an operation to be performed by the variable-length data and a delimiter portion designating a delimiter;

address generating means for sequentially outputting addresses to obtain said variable-length data;

instruction decoding means coupled to said instruction storage means, for decoding said operation portion of said one instruction output from said instruction storage means;

data processing means coupled to said instruction decoding means, for consecutively processing variable-length data in accordance with said decoded operation portion, the variable length data being consecutively read out by using the addresses output from said address generating means;

delimiter detecting means coupled to said instruction storage means, for outputting a coincidence signal upon detecting that a delimiter of said variable-length data which coincides with the delimiter designated by said delimiter portion of said one instruction is present in said consecutively read out variable-length data; and

control means coupled to said delimiter detecting means, for ending said consecutive processing of variable-length data performed in accordance with said decoded operation portion in response to the coincidence signal from said delimiter detecting means.