Duplex data processing system with programmable bus configuration

• US 4,975,838 A
• Filed: 04/09/1987
• Issued: 12/04/1990
• Est. Priority Date: 04/09/1986
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Mizuno, Kenichi, Morita, Takashi, Ikeda, Teruo
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/036,509
• Time in Patent Office: 1,335 Days
• Field of Search: 371/9, 371/9.1, 371/11.1, 371/11.3, 324/73 R, 364/200 MS File, 364/900 MS File
• US Class Current: 709/221
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage
• CPC Class Codes: H04Q 3/54558 Redundancy, stand-by

Abstract

A duplex data processing system includes two processors each provided with a bus connecting unit which disconnects the associated CPU bus from the cross connection bus in a separate mode or connects the CPU bus to the cross connection bus in a duplex mode. The system operates with a logically unified CPU bus through the connection of the internal CPU buses by the two bus connecting units in both processors.

Claims

1. A duplex data processing system comprising:

two processor systems, one of which is operating as an active system and the other of which is operating as a stand-by system, respectively, in a duplex system mode of operation, each processor system including a central processing unit (CPU), a memory unit and an input/output controller interconnected by a CPU bus, the memory units in the two processor systems operating with the same address mapping;

a cross connection bus provided between said two processor systems; and

bus connecting means provided in each of said processor systems and connected to the CPU bus within said processor system and to said cross connection bus, for disconnecting said two processor systems to establish a Separate mode of operation in which said two processor systems operate independently and for interconnecting said two processor systems via said cross connecting bus to establish a Duplex mode of operation in which said two processor systems are arranged in duplex configuration such that the CPU of the active system can access the respective memory units in both processor systems simultaneously in response to commands from the CPU in the active processor system, each bus connecting means including means operative in said Separate mode of operation for disconnecting the CPU bus in its processor system from the CPU bus in the other processor system by breaking the connection between the CPU bus in its processor system and said cross connection bus, and means operative in said Duplex mode of operation for connecting the CPU bus in its processor system to the CPU bus in the other processor system by making the connection of its CPU bus through said cross connecting bus to the CPU bus in the other processor system.

2. A duplex data processing system according to claim 1, wherein said bus connecting means comprises:

an address decoder circuit connected to receive address information from a CPU or input/output controllers operating as a bus master to control said connected CPU buses over said CPU bus, for analyzing the address information to determine an access destination of said bus master, and for producing access destination identification information;

a bus master monitoring circuit for detecting whether said bus master resides in its processor system or in the other processor system, and for producing resultant detection information;

mode setting means connected to receive a mode setting command from the CPU in the active processor system over said CPU bus for establishing a Separate mode or Duplex mode, and for producing mode information indicative thereof;

an address bus gating circuit which includes a first gate connected between an address bus of said CPU bus and an address bus of said cross connection bus, and means responsive to detected information from said bus master monitoring circuit and mode information from said mode setting means for controlling said first gate depending on said received information;

a control bus gating circuit which includes a second gate connected between a control bus of said CPU bus and a control bus of said cross connection bus, and means responsive to detected information from said bus master monitoring circuit and mode information from said mode setting means for controlling said second gate depending on said received information;

a data bus gate control signal generator connected to receive decoded information from said address decoder circuit, detected information from said bus master monitoring circuit and mode information from said mode setting means, for determining the data bus direction depending on said received information, and for producing determined information indicative thereof; and

a data bus gating circuit which includes a third gate connected between a data bus of said CPU bus and a data bus of said cross connection bus, and means responsive to mode information from said mode setting means and determined information from said data bus gate control signal generator for controlling said third gate depending on said received information.

3. A duplex data processing system according to claim 2, wherein said mode setting means comprises:

a first flip-flop connected to said CPU bus for storing a Separate mode indication or a Duplex mode indication;

a second flip-flop connected to said CPU bus for storing a Double Write mode indication or Single Write mode indication; and

a third flip-flop connected to said CPU bus for storing a Read Active System mode indication or Read Stand-by System mode indication.

4. A duplex data processing system according to claim 2, wherein said bus connecting means further comprises:

a data acknowledge circuit which communicates a data acknowledge signal issued by said access destination of said bus master from said CPU bus to said cross connection bus.

5. A duplex processing system according to claim 1, wherein said bus connecting means in the processor active system includes a first mode setting means connected to receive a mode setting command from the CPU in the active processor system over the CPU bus therein for producing mode information indicative of a Separate mode or Duplex mode of operation;

and the bus connecting means in the stand-by processor system includes second mode setting means connected to receive and store mode information from said first mode setting means;

said CPU in said stand-by processor system including means responsive to mode information in said second mode setting means which indicates a Duplex mode of operation for disconnecting the CPU in said stand-by processor system from the CPU bus therein.

7. A duplex processing system according to claim 5, wherein said bus connecting means in the stand-by processor system includes mode setting means for producing mode information indicating whether the bus connecting means is operating in the Separate mode or the Duplex mode;

and said CPU in said stand-by processor system includes means responsive to mode information in said mode setting means which indicates a Duplex mode of operation for disconnecting the central processing unit in said stand-by processor system from the CPU bus therein.

6. A duplex data processing system with programmable bus configuration comprising:

a pair of processor systems, each processor system including a central processing unit (CPU), a memory unit, an input/output controller, and a CPU bus connecting said central processing unit, memory unit and input/output controller, the memory units in the pair of processor systems operating with the same address mapping;

a cross connecting bus provided between said pair of processor systems; and

bus connecting means provided in each of said processor systems and connected to said CPU bus and said cross connecting bus and adapted to operate in a Separate mode in which said CPU buses of said pair of processor systems are separated and in a Duplex mode in which one processor system operates as an active processor system and the other processor system operates as a stand-by processor system and each CPU of said pair of processor systems is connected via said cross connecting bus so that the central processing unit in the active processor system can access the memory units in both processor systems simultaneously in response to a command from said central processing unit in said one processor system, said bus connecting means including means operating in said Separate mode for disconnecting the CPU bus from said cross connecting bus, and in said Duplex mode for connecting said CPU buses of said processor systems through said cross connecting bus to form a logically unified system.