Method of improving a placement in layout design

• US 4,975,854 A
• Filed: 05/22/1987
• Issued: 12/04/1990
• Est. Priority Date: 05/23/1986
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yabe, Shoji
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/053,013
• Time in Patent Office: 1,292 Days
• Field of Search: 364/300, 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A location method in a layout design improves the efficiency of wiring connections among elements. For each row of cell units, the number of cells in variable length blocks and the number of terminals in each block are identified. After counting the available empty cells, the number of empty cells required by each block is calculated based on the number of cells and terminals in the block. For ech row of cells the empty cells are distributed to the blocks. The blocks are then located accordingly on the base structure.

Claims

1. A layout placement method for a wiring grid with a plurality of cell rows, separated by wiring regions, each cell row having a plurality of cells, the method comprising the steps of:

(a) for each cell row inputting to a logic connection information file a number and type of variable size blocks, each block containing an integral number of cells and reading from a preprogrammed library a required number of cells for each block type input for a row,

(b) inputting to the logic connection information file a number of block terminals for each block,

(c) counting a number of empty cells of each cell row,

(d) calculating a number of required empty cells for each row from the number of blocks, the number of block terminals and the number of empty cells, by;

(i) determining an average cell row terminal density equal to the total number of terminals in the cell row divided by the total number of cells in the cell row, and

(ii) determining the number of required empty cells for a block by finding the difference between the number of block terminals in the cell row divided by the average terminal density of the cell row and the number of cells in the block,

(e) calculating for each row one of an excess and deficiency of the required empty cells from the difference between the number of empty cells and the number of required empty cells,

(f) distributing blocks on the wiring grid to compensate for the calculated one of the excess and deficiency, and

(g) locating the distributed blocks on a base structure of the wiring grid.

2. The method of claim 1 further comprising the steps of:

locating variable length blocks in sequence from a first end to a second end along a cell row,

locating empty cells not distributed to blocks on a first end of the cell row,

locating empty cells distributed to a block on a second end of the block, and

shifting blocks along the cell row to accommodate the location of empty cells.

3. The method of claim 1 further comprising interconnecting block terminals after said locating step.

4. The method of claim 1 wherein the wiring grid comprises a model for a semiconductor device.

5. The method of claim 1 wherein the wiring grid comprises a model for a printed circuit.

6. The method of claim 1 wherein the wiring grid comprises a model for an LSI circuit.

7. The method of claim 1 wherein the wiring grid comprises a model for a VLSI circuit.

8. A layout placement method for a wiring grid with a plurality of cell rows, separated by wiring regions, each cell row having a plurality of cells, the method comprising the steps of:

(a) for each cell row inputting to a logic connection information file a number and type of variable size blocks, each block containing an integral number of cells and reading from a preprogrammed library a required number of cells for each block type input for a row, wherein each block begins with a non-empty cell and includes an integral number of adjacent cells to the beginning of the next block,

(b) inputting to the logic connection information file a number of block terminals for each block,

(c) counting a number of empty cells of each cell row,

(d) calculating a number of required empty cells for each row from the number of blocks, the number of block terminals and the number of empty cells, by;

(i) determining an average cell row terminal density equal to the total number of terminals in the cell row divided by the total number of cells in the cell row, and

(ii) determining the number of required empty cells for a block by finding the difference between the number of block terminals in the cell row divided by the average terminal density of the cell row and the number of cells in the block,

(e) calculating for each row one of an excess and deficiency of the required empty cells from the difference between the number of empty cells and the number of required empty cells,

(f) distributing blocks on the wiring grid to compensate for the calculated one of the excess and deficiency, and

(g) locating the distributed blocks on a base structure of the wiring grid,

(h) maintaining a record containing for each block in a cell row the number of empty cells, the number of required empty cells, the excess and deficiency of empty cells, and further containing a number of empty cells located at a first end of the cell row before the first cell in the first block, and

(i) distributing empty cells at the first end of the cell row to each block having a deficiency of empty cells.

9. The method recited in claim 8 further comprising the steps of:

locating variable length blocks in sequence from a first end to a second end along a cell row,

locating empty cells not distributed to blocks on a first end of the cell row,

locating empty cells distributed to a block on a second end of the block, and

shifting blocks along the cell row to accommodate the location of empty cells.

10. The method of claim 8 further comprising interconnecting blocks terminals after said locating step.

11. The method of claim 8 wherein the wiring grid comprises a model for at least one of a semiconductor device, a printed circuit, an LSI circuit, and a VLSI circuit.