Dual port memory device with tag bit marking

• US 4,975,872 A
• Filed: 11/13/1989
• Issued: 12/04/1990
• Est. Priority Date: 11/17/1988
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Zaiki, Koji
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/435,049
• Time in Patent Office: 386 Days
• Field of Search: 365/230.05, 365/49, 365/230.06, 365/189.07, 365/189.05, 365/233, 364/200 MS File, 364/900 MS File
• US Class Current: 365/49.1
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory device comprises an address input, first decoder for decoding an address input applied to the address input means, two-port data storage for storing data, a tag field provided for each of word areas of the data storage means, means for reading data through the first port of the data storage means, data input/output means for writing in and reading out data through the second port of the data storage means, selecting means for selecting data read out through the first port of the data storage means or data externally inputted through the data input/output means, second decoding means for decoding an output data from the selecting means into an address, and control means for controlling reading out of data through the first port of the data storage means, controlling writing in and reading out of data through the second port of the data storage means, and operating in synchronism with an externally supplied clock signal for controlling marking in the tag fields selected sequentially according to address data inputted from the outside through the data input/output means.

Claims

1. A memory device comprising:

address input means;

first decoding means for decoding an address input applied to said address input means;

two-port data storage mean for storing data;

a tag field provided for each of word areas of said data storage means;

means for reading data through the first port of said data storage means;

data input/output means for writing in and reading out data through the second port of said data storage means;

selecting means for selecting data read out through the first port of said data storage means or data externally inputted through said data input/output means;

second decoding means for decoding an output data from said selecting means into an address; and

control means for controlling reading out of data through the first port of said data storage means, controlling writing in and reading out of data through the second port of said data storage means, and operating in synchronism with an externally supplied clock signal for controlling marking in the tag fields selected sequentially according to address data inputted from the outside through said data input/output means.

2. A memory device according to claim 1, wherein the address data inputted from the outside through said data input/output means is an address of a first list element to be marked.

3. A memory device according to claim 1, wherein said selecting means first selects the address data inputted from the outside through said data input/output means and thereafter selects the data read out through the first port of said data storage means.

4. A memory device according to claim 1, wherein the marking operation is completed upon completion of a comparison made in comparing means between the data read out through the first port of said data storage means and marking end data.

5. A memory device according to claim 1, wherein marking in said tag field is carried out in parallel with the writing in and reading out of data through the second port of said data storage means.