Variable-capacitance type sensor and variable-capacitance type sensor system using the same

• US 4,977,480 A
• Filed: 09/13/1989
• Issued: 12/11/1990
• Est. Priority Date: 09/14/1988
• Status: Expired due to Fees

• Current Assignee: Fuji Xerox Manufacturing Company Limited (Fujifilm Holdings Corporation)
• Original Assignee: Fuji KOKI Manufacturing Company Limited
• Inventors: Nishihara, Toshihiko
• Primary Examiner(s): GRIFFIN, DONALD
• Application Number:
  US07/406,960
• Time in Patent Office: 454 Days
• Field of Search: 73/701, 73/718, 73/724, 361/283
• US Class Current: 361/283.4
• CPC Class Codes: G01L 9/0072 using variations in capacitance
• CPC Class Codes: G01L 9/125 with temperature compensating means non electric temperature compensating means G01L19/04

Abstract

A constant-capacitance capacitor is series-connected with a variable-capacitance capacitor whose capacitance varies with the pressure. The other end of the variable-capacitance capacitor is connected to the ground potential terminal of a D.C. power source. The terminal voltage of the variable-capacitance capacitor is compared with a threshold voltage provided by the D.C. power source by means of a comparator. An output voltage of the comparator is stored into a memory in synchronism with a clock pulse signal. An output voltage of the memory is integrated by an integrator. An output voltage of the integrator is supplied to a buffer amplifier for lowering the signal source impedance with respect to the output voltage. An output voltage obtained from the buffer amplifier is fed back to the other end of the constant-capacitance capacitor and at the same time supplied to an output terminal.

Claims

1. A variable-capacitance type sensor system comprising:

series-connected first and second capacitors, said second capacitor being connected at one end to one end of said first capacitor, and one of said first and second capacitors acting as a pressure-capacitance transducer;

detecting means connected to a connection node between said first and second capacitors, for detecting a terminal voltage of said second capacitor input via said connection node;

a memory connected to an output terminal of said detecting means, for receiving an output of said detecting means in synchronism with a clock signal and storing the same;

an integrator connected between an output terminal of said memory and the other end of said first capacitor, for charging said first and second capacitors which are serially connected according to an output voltage derived by integrating the output of said memory, the output voltage of said integrator varying in inverse proportion to the capacitance of said first capacitor when said first capacitor acts as the transducer, and in proportion to the capacitance of said second capacitor when said second capacitor acts as the transducer; and

a output terminal connected to the output terminal of said integrator, for outputting the output voltage of said integrator.

2. The system according to claim 1, wherein said second capacitor includes a planar electrode capacitor which has fixed and movable electrodes whose electrode surfaces are set to face each other and whose capacitance varies with variation in a distance between said electrodes in a direction perpendicular to said electrodes.

3. The system according to claim 1, wherein said second capacitor includes:

a planar electrode capacitor which has fixed and movable electrodes with the electrode surfaces thereof set to face each other and whose capacitor varies with the vertical distance between said facing electrodes; and

a constant-capacitance capacitor series-connected to said planar electrode capacitor, said second capacitor having a capacitance equal to the resultant capacitance of said planar electrode capacitor and said constant-capacitance capacitor.

4. The system according to claim 1, further comprising charging/discharging selection means for alternately forming a charging circuit for charging said series-connected first and second capacitors by an output voltage of said integrator and a discharging circuit for discharging said first and second capacitors.

5. The system according to claim 4, wherein said charging/discharging selection means includes:

first switching means connected between said integrator and the other end of said first capacitor, for selectively connecting said series-connected first and second capacitors to said integrator so as to selectively form said charging circuit for charging said series-connected first and second capacitors by an output voltage of said integrator;

second switching means connected in parallel with said first and second capacitors, for selectively connecting the other end of said first capacitor and said connection node to the other end of said second capacitor so as to selectively form said discharging circuit for discharging said first and second capacitors; and

switching controlling means for periodically and alternately activating said first and second switching means.

6. The system according to claim 5, wherein

said first switching means includes a first electronic switch connected between said integrator and the other end of said first capacitor;

said second switching means includes;

a second electronic switch connected between the other ends of said first and second capacitors; and

a third electronic switch connected between said connection node and the other end of said second capacitor; and

said switching controlling means includes;

clock pulse generating means for generating a clock pulse of a predetermined period;

first control signal generating means connected to said clock pulse generating means, for deriving a first control signal for turning on said first electronic switch from the clock pulse; and

second control signal generating means connected to said first control signal generating means, for deriving a second control signal for turning on said third electronic switch by inverting said first control signal, said second control signal being supplied as said clock signal to said memory.

7. A variable-capacitance type sensor system comprising:

first and second capacitors, said second capacitor being connected at one end to one end of said first capacitor;

selection means connected between the other ends of said first and second capacitors, for sequentially and periodically completing one of a charging circuit for charging said first capacitor, a parallel circuit for transferring the charge of said first capacitor to said second capacitor, and a discharging circuit for discharging the charge of said first and second capacitors;

detecting means connected to the other end of said second capacitor, for detecting a voltage occurring across said first and second capacitors when said parallel circuit of said first and second capacitors is completed by said selection means;

a memory connected to an output terminal of said detecting means, for receiving an output of said detecting means in synchronism with a clock signal and storing the same;

an integrator connected between an output terminal of said memory and the other end of said first capacitor, for supplying an output voltage derived by integrating the output of said memory to said first capacitor when said charging circuit for said first capacitor is completed by said selection means, the output voltage of said integrator varying one of (a) in proportion to the capacitance of said second capacitor and (b) in inverse proportion to the capacitance of said first capacitor; and

an output terminal connected to the output terminal of said integrator, for outputting the output voltage of said integrator.

8. The system according to claim 7, wherein said switching means includes:

a first electronic switch connected between said integrator and the other end of said first capacitor;

a second electronic switch connected between the other ends of said first and second capacitors;

a third electronic switch connected between the other end of said second capacitor and a ground potential point and turned on and off in synchronism with said first electronic switch; and

control means for selectively turning on and off said first to third electronic switches, said charging circuit being formed when said first and second electronic switches are turned on and said third electronic switch is turned off, said parallel circuit being formed when said first and second switches are turned off and said third electronic switch is turned on, and said parallel circuit being formed when said first to third electronic switches are all turned off.

9. The system according to claim 8, wherein said control means includes:

clock pulse generating means for generating a clock pulse of a predetermined period;

first control signal generating means, connected to said clock pulse generating means, for deriving a first control signal for turning on said first and third electronic switches from said clock pulse; and

second control signal generating means, connected to said clock pulse generating means and said first control signal generating means, for deriving a second control signal for turning on said second electronic switch from said clock pulse and said first control signal, said second control signal being supplied as the clock signal to said memory with a predetermined time delay.

10. The system according to claim 7, wherein said first capacitor includes a planar electrode capacitor which has a fixed electrode and a movable electrode with the electrode surfaces thereof set to face each other and whose capacitance varies as a distance between said fixed and movable electrodes in a direction perpendicular to said fixed and movable electrodes varies;

and

an output voltage of said integrator varies in inverse proportion to variation in the capacitance of said first capacitor.

11. The system according to claim 7, wherein said second capacitor includes a planar electrode capacitor which has fixed and movable electrodes with the electrode surfaces thereof set to face each other and whose capacitance varies as a distance between said fixed and movable electrodes in a direction perpendicular to said fixed and movable electrodes varies;

and

an output voltage of said integrator varies in proportion to variation in the capacitance of said second capacitor.

12. The system according to claim 7, wherein said second capacitor includes:

a planar electrode capacitor which has fixed and movable electrodes with the electrode surfaces thereof set to face each other and whose capacitance varies as a distance between said fixed and movable electrodes in a direction perpendicular to said fixed and movable electrodes varies;

a constant-capacitance capacitor series-connected to said planar electrode capacitor, said second capacitor having a resultant capacitance of the capacitances of said planar electrode capacitor and said constant-capacitance capacitor; and

an output voltage of said integrator varies in proportion to variation in the capacitance of said second capacitor.

13. The system according to claim 7, wherein said first capacitor is constituted by a parallel circuit of a first fixed capacitor and a first variable capacitor;

and

said second capacitor is constituted by a series circuit of a second fixed capacitor and a second variable capacitor.

14. The system according to claim 13, wherein said first and second variable capacitors are each constituted by a planar electrode capacitor which has fixed and movable electrodes with the electrode surfaces thereof set to face each other and whose capacitance varies as a distance between said fixed and movable electrodes in a direction perpendicular to said fixed and movable electrodes varies.

15. The system according to claim 14, wherein the electrode surface of said fixed electrode of said planar electrode capacitor is divided into a plurality of electrode regions;

said first variable capacitor is constituted by a first electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor; and

said second variable capacitor is constituted by a second electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor.

16. The system according to claim 14, wherein the electrode surface of said fixed electrode of said planar electrode capacitor is divided into a plurality of electrode regions;

said parallel circuit of said first variable capacitor and said fixed capacitor is constituted by a first electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor; and

said second variable capacitor is constituted by a second electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor.

17. The system according to claim 14, wherein the electrode surface of said fixed electrode of said planar electrode capacitor is divided into a plurality of electrode regions;

said parallel circuit of said first variable capacitor and said first fixed capacitor is constituted by a first electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor; and

said series circuit of said second capacitor and said second fixed capacitor is constituted by a second electrode region of said fixed electrode of said planar electrode capacitor and said movable electrode of said planar electrode capacitor.

18. A variable-capacitance type sensor comprising:

a planar electrode capacitor which has fixed and movable electrodes with surfaces thereof set to face each other and whose static capacitance varies according to a variation in a distance between the electrodes in a direction perpendicular to the electrodes; and

a fixed constant-capacitance capacitor serially connected to the planar electrode capacitor;

wherein capacitance of the variable-capacitance type sensor, which varies according to a pressure applied thereto, is a resultant synthesized capacitance of the static capacitance of the planar electrode capacitor and a capacitance of the constant-capacitance capacitor, thus resulting in an improved output characteristic for the variable-capacitance type sensor.