Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

• US 4,977,542 A
• Filed: 08/30/1989
• Issued: 12/11/1990
• Est. Priority Date: 08/30/1988
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arimoto, Kazutami, Tsukude, Masaki, Ooishi, Tsukasa, Matsuda, Yoshio, Fujishima, Kazuyasu
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/400,898
• Time in Patent Office: 468 Days
• Field of Search: 365/207, 365/189.01, 365/210, 365/238, 365/149
• US Class Current: 365/207
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns for storing information charge;

a plurality of bit line pairs, each comprising a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;

a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;

read means for selecting any of said word lines by applying a potential thereto, and reading the respective information charges of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of each said bit line pair when said read means reads the information charges of the memory cells; and

potential applying means for applying a potential for compensating for change in a potential of the bit lines to said bit lines, said change being caused by rise of a potential of the word line selected by said read means.

2. A semiconductor memory device in accordance with claim 1, wherein

each said memory cell comprises a first transistor connected through a first connection portion to the corresponding bit line, and the potential change appearing on the bit lines when the word line is selected by said read means is caused by a capacitance coupling between the word line to which the potential is applied and said first connection portion of said transistor included in the memory cells from which reading is effected.

3. A semiconductor memory device in accordance with claim 1, wherein

each said bit line pair has two twisted portions for each said bit line and said potential applying means comprises

a plurality of dummy cells each including a second transistor connected through a second connection portion to the corresponding bit line, two dummy cells being provided for each bit line,

a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs and connected to the corresponding dummy cells, a predetermined potential being applied thereto, and

potential removing means responsive to the selection of the word line by said read means, for removing said predetermined potential applied to the dummy word line connected to any of the dummy cells provided corresponding to the bit lines to which the memory cells connected to the selected word line are connected.

4. A semiconductor memory device in accordance with claim 3, wherein

a potential change in each bit line caused by capacitance coupling between any of the word lines to which said predetermined potential is applied and said second connection portion of said second transistor is equal to a potential change appearing between the respective bit lines when the word line is selected by said read means.

5. A semiconductor memory device in accordance with claim 4, wherein

the number of said dummy word lines is four, and two dummy word lines are provided for a twisted portion of a predetermined bit line pair out of said bit line pairs.

6. A semiconductor memory device in accordance with claim 5, further comprising

a plurality of word driver circuits provided corresponding to the respective word lines, wherein

said word lines are divided into four word line groups according to the positions of the twisted portions of said bit line pairs and said word driver circuits are divided into four word driver circuit groups corresponding to said word line groups, to drive the corresponding word lines.

7. A semiconductor memory device in accordance with claim 5, further comprising

a plurality of word driver circuits provided corresponding to the respective word lines, wherein

said word lines are divided into four word line groups according to positions of the twisted portions of said bit line pairs and said word driver circuits are divided into four word driver circuit groups corresponding to said word line groups, the word driver circuits of the two word driver circuit groups out of said four word driver circuit groups drive the corresponding word lines, and the word driver circuits of the other two word driver circuit groups drive the word lines adjacent to the corresponding word lines.

8. A semiconductor memory device in accordance with claim 1, wherein

the number of twisted portions of said bit line pairs is two for each said bit line pair, and

said potential applying means comprises

a plurality of dummy cells each provided for each bit line, including a second transistor connected through a second connection portion to the corresponding bit line,

a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs and connected to the corresponding dummy cells, a predetermined potential being applied thereto, two dummy word lines being provided at a twisted portion of a predetermined bit line pair out of said bit line pairs, a dummy word line connected with a dummy cell corresponding to one bit line of the bit line pair and a dummy word line connected to a dummy cell corresponding to the other bit line of the bit line pair existing at different twisted portions of said bit line pair, and

potential removing means responsive to selection of the word line by said read means, for removing said predetermined potential of the dummy word line connected to the dummy cell provided corresponding to the bit line to which the memory cells connected to the selected word line are connected.

9. A semiconductor memory device in accordance with claim 8, wherein

the respective bit lines of the adjacent first and second bit line pairs correspond to one and the other bit lines, one of the first dummy word lines provided at one of the twisted portions of said first bit line pair is connected to the dummy cell provided at said one bit line of said first bit line pair, the other line of said first dummy word line is connected to the dummy cell provided at the other bit line of said second bit line pair, the other one of the second dummy word line provided at the other twisted portion of said first bit line pair is connected to the dummy cell provided at said other bit line of said first bit line pair, the other one of said second dummy word line is connected to the dummy cell provided at said one bit line of said second bit line pair,

said potential removing means is responsive to the selection of the word line by said read means and removes simultaneously said predetermined potential applied to said one of said first dummy word lines and said other of said second word lines, or to said other of said first dummy word lines and said one of said second dummy word lines.

10. A semiconductor memory device in accordance with claim 9, further comprising a plurality of word driver circuits provided corresponding to the respective word lines, wherein

said word lines are divided into four word line groups according to positions of twisted portions of the bit lines, said word driver circuits are divided into four word driver circuit groups corresponding to said word line groups, the word driver circuits of two word driver circuit groups out of said four word driver circuit groups drive the corresponding word lines and the word driver circuits of the other two word driver circuit groups drive the word lines adjacent to the corresponding word lines.

11. A semiconductor memory device in accordance with claim 1, further comprising

a semiconductor substrate having a main surface, on which said memory cells and said word lines are formed,

an insulating film covering said memory cells formed on said semiconductor substrate,

each said bit line pair being formed on said insulating film and one bit line of said pair being connected through a conductor having a section formed like the letter V at said twisted portion.

12. A semiconductor memory device in accordance with claim 11, wherein

part of said word lines are formed on the main surface of said semiconductor substrate through the insulating film, said conductor is polysilicon formed on an upper portion of the memory cells close thereto from above the main surface of said semiconductor substrate in a region between two word lines out of the word lines formed on the main surface of said semiconductor substrate, and one bit line of said pair is connected to said polysilicon in said upper portion.

13. A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns, for storing information charge;

a first memory cell area where part of said memory cells are formed;

a second memory cell area where another part of said memory cells are formed;

a first dummy cell area formed between said first memory cell area and said second memory cell area;

a third memory cell area formed adjacent to said second memory cell area, part of said memory cells being formed in said third memory cell area;

a fourth memory cell area where part of said memory cells are formed;

a second dummy cell area formed between said third memory cell area and said fourth memory cell area;

a plurality of bit line pairs each including a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;

a plurality of word lines provided corresponding to the respective columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;

read means for selecting any of said word lines by applying a potential thereto, and reading the information charge of each of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means;

a plurality of dummy cells, at least one dummy cell being provided for each bit line in said first or second dummy cell area;

a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs, and connected to the corresponding dummy cells, a predetermined potential being applied to said dummy word lines; and

potential cancel means responsive to the selection of the word line by said read means, for cancelling the application of said predetermined potential to the dummy word line connected to any of the dummy cells provided with respect to the bit line to which the memory cell connected to the selected word line is connected.

14. A semiconductor memory device in accordance with claim 13, wherein

the number of the twisted portions of said respective bit line pairs is two for each said bit line pair, said twisted portions of alternate bit line pairs are provided in said first and second dummy cell areas, and one of said twisted portions of each of the other bit line pairs is provided between said second memory cell area and said third memory cell area.

15. A semiconductor memory device in accordance with claim 13, further comprising:

a plurality of word driver circuits provided corresponding to the respective word lines, wherein

said word lines are divided into four word line groups corresponding to said first to fourth memory cell areas, and said word driver circuits are divided into four word driver circuit groups corresponding to said word line groups, to drive the corresponding word lines.

16. A semiconductor memory device in accordance with claim 15, wherein

each of said first to fourth memory cell areas is further divided into two memory cell areas, and said word line groups are divided into eight word line groups corresponding to the divided eight memory cell areas.

17. A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns, for storing information charge;

a first memory cell area where part of said memory cells are formed;

a second memory cell area formed adjacent to said first memory cell area part of said memory cells being formed in said second memory cell area;

a third memory cell area where part of said memory cells are formed;

a first dummy cell area formed between said second and third memory cell areas;

a fourth memory cell area formed adjacent to said first dummy cell area, part of said memory cells being formed in said fourth memory cell area;

a fifth memory cell area adjacent to said fourth memory cell area, part of said memory cells being formed in said fifth memory cell area;

a sixth memory cell area formed adjacent to said fifth memory cell area, part of said memory cells being formed in said sixth memory cell area;

a seventh memory cell area where part of said memory cells are formed;

a second dummy cell area formed between said sixth and seventh memory cell areas;

an eighth memory cell area formed adjacent to said memory cell area, part of said memory cells being formed in said eighth memory cell area;

a plurality of bit line pairs each including a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;

a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;

read means for selecting any of said word lines by applying a potential thereto, and reading the information charge of each of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means;

a plurality of dummy cells, at least one dummy cell being provided for each said bit line in said first or second dummy cell area;

a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs, and connected to the corresponding dummy cells, a predetermined potential being applied to said dummy word lines; and

potential cancel means responsive to the selection of the word line by said read means, for cancelling the application of said predetermined potential to the dummy word line connected to any of the dummy cells provided with respect to the bit line to which the memory cell connected to the selected word line is connected.

18. A semiconductor memory device in accordance with claim 17, wherein

the number of the twisted portions of said bit line pairs is two for each said bit line pair, said twisted portions of alternate bit line pairs are provided in said first and second dummy cell areas, and one of said twisted portions of each of the other bit line pairs is formed in an area between said fourth and fifth memory cell areas.

19. A semiconductor memory device in accordance with claim 17, further comprising:

a plurality of word driver circuits provided corresponding to the respective word lines, wherein

said word lines are divided into eight word line groups corresponding to said first to eighth memory cell areas, and said word driver circuits are divided into eight word driver circuit groups corresponding to said word line groups, to drive the corresponding word lines.

20. A semiconductor memory device comprising:

a semiconductor substrate having a main surface;

a plurality of memory cells formed on the main surface of said semiconductor substrate and arranged in a matrix of rows and columns, for storing information charge;

an interlayer insulating film formed on the main surface of said semiconductor substrate to cover said memory cells;

a plurality of bit line pairs formed on said interlayer insulating film, each said bit line pair being formed of a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;

a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;

read means for selecting any of said word lines by applying a potential thereto, and reading the information charges of the memory cells connected to the selected word line onto the respective bit lines of said bit line pairs; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means,

one bit line of each said pair being connected at said twisted portion through a conductor having a section formed like the letter V.

21. A semiconductor memory device in accordance with claim 20,

part of said word lines are formed on the main surface of said semiconductor substrate through the insulating film, said conductor is polysilicon formed on an upper portion of the memory cells close thereto from above the main surface of said semiconductor substrate in a region between two word lines out of the word lines formed on the main surface of said semiconductor substrate, and one bit line of said pair is connected to said polysilicon in said upper portion.