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Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips

  • US 4,978,639 A
  • Filed: 01/10/1989
  • Issued: 12/18/1990
  • Est. Priority Date: 01/10/1989
  • Status: Expired due to Fees
First Claim
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1. A method for simultaneously producing plated via-holes and wraparound plating in semiconductor chips formed from a semiconductor wafer having a front surface including a plurality of metal pads, a back surface, and a thickness measured from the front surface to the back surface, the method comprising the steps of:

  • (i) forming via-holes and grooves in the wafer from its front surface, the grooves defining the boundaries of individual semiconductor chips, the grooves and the via-holes extending from the front surface of the wafer to a depth within the wafer which is less than the total thickness of the wafer, the via-holes being formed through selected metal pads, the grooves and via-holes each having walls and a floor;

    (ii) simultaneously plating the walls and floor of the grooves and the via-holes with conductive metal;

    (iii) removing a portion of the back surface of the semiconductor wafer to a depth sufficient to remove the floor of both the grooves and the via-holes, thereby exposing the metal plating located on the walls of both the via-holes and the grooves, thus separating the individual chips; and

    (iv) plating the back surface of the individual chips with conductive metal.

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