Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips

• US 4,978,639 A
• Filed: 01/10/1989
• Issued: 12/18/1990
• Est. Priority Date: 01/10/1989
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avantek Inc. (HP Inc.)
• Inventors: Chan, Simon S., Day, Ding-Yuan S., Lee, Adrian C., Hua, Chang-Hwang
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/295,300
• Time in Patent Office: 707 Days
• Field of Search: 437/226, 437/227, 437/230, 437/245, 437/974, 148/DIG. 28, 148/DIG. 135, 156/643, 156/656
• US Class Current: 438/465
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.

Claims

1. A method for simultaneously producing plated via-holes and wraparound plating in semiconductor chips formed from a semiconductor wafer having a front surface including a plurality of metal pads, a back surface, and a thickness measured from the front surface to the back surface, the method comprising the steps of:

(i) forming via-holes and grooves in the wafer from its front surface, the grooves defining the boundaries of individual semiconductor chips, the grooves and the via-holes extending from the front surface of the wafer to a depth within the wafer which is less than the total thickness of the wafer, the via-holes being formed through selected metal pads, the grooves and via-holes each having walls and a floor;

(ii) simultaneously plating the walls and floor of the grooves and the via-holes with conductive metal;

(iii) removing a portion of the back surface of the semiconductor wafer to a depth sufficient to remove the floor of both the grooves and the via-holes, thereby exposing the metal plating located on the walls of both the via-holes and the grooves, thus separating the individual chips; and

(iv) plating the back surface of the individual chips with conductive metal.

2. The method as recited in claim 1 wherein the steps of forming the grooves and via-holes is by applying photoresist to the front surface of the wafer, exposing and developing the photoresist using a pattern to create a mask, and etching the grooves and via-holes using this mask.

3. The method as recited in claim 2 in which the grooves and via-holes are etched by reactive ion etching.

4. The method as recited in claim 1 wherein the steps of depositing the conductive metal plating on the walls and floors of the grooves and on the walls and floors of the via-holes includes the steps of electroless depositing a first layer of conductive metal on walls and floor of the grooves and the via-holes and then depositing on the first layer of conductive metal a second layer of conductive metal by electrolytic plating.

5. The method as recited in claim 4 wherein the step of depositing the first layer of conductive metal comprises electroless plating a layer of palladium.

6. The method as recited in claim 4 wherein the step of depositing the second layer of conductive metal comprises the step of electrolytically plating one or more metals selected from the group comprising gold and platinum.

7. The method as recited in claim 4 wherein the electrolytic step further comprises electrolytic plating while ultrasonically agitating the electrolyte.

8. The method as recited in claim 1 wherein the step of plating the conductive metal on the back surface of the chips comprises the step of electroless plating the back surface with the conductive metal.