CMOS digital level shifter circuit

• US 4,978,870 A
• Filed: 07/19/1989
• Issued: 12/18/1990
• Est. Priority Date: 07/19/1989
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Tu, Nang-Ping, Chen, Ming-Daw
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Wambach, Margaret Rose
• Application Number:
  US07/382,136
• Time in Patent Office: 517 Days
• Field of Search: 307/443, 307/448, 307/451, 307/475, 307/482, 307/272.1, 307/272.2, 307/264
• US Class Current: 326/68
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

Claims

1. In a digital level shifting circuit having a single voltage supply and inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inserted signal, the improvement comprising:

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage to said input inverter means, and

latch means energized by said voltage supply and having tow branches, each of said branches having transistor means, each transistor means having a commonly connected drain and a commonly connected gate, the commonly connected gate of one of said transistor means being connected to receive said inverted signal, said transistor means in each of said branches comprising a complementary transistor pair comprising an NMOS transistor and a PMOS transistor, the commonly connected gate of the other one of said transistor means being connected to receive said input signal, whereby at the commonly connected drain of the other transistor means is produced a shifted voltage characterized by a second peak voltage level corresponding to the voltage of said voltage supply.

2. The improvement of claim 1 wherein said second peak voltage is greater than said first peak voltage.

3. The improvement of claim 1 wherein said voltage generator circuit means comprises:

capacitor means;

a source follower transistor connected between said voltage supply source and said capacitor means, said source follower transistor having a gate connected to receive said input signal; and

a directional switching means connected between said source follower transistor and said capacitor means for preventing discharge of said capacitor means through said source follower means, whereby said capacitor means compensates for fluctuations in the source voltage of said source follower transistor, said capacitor means being further connected to said input inverter so as to furnish said internally generated supply voltage to said input inverter.

4. The improvement of claim 2 wherein said internally generated supply voltage furnished by said voltage generator circuit means is less than the voltage of said voltage supply.

5. In a digital level shifting circuit having a single voltage supply and input inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inverter signal, the improvement comprising:

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage to said input inverter means, and

latch means energized by said voltage supply and having two branches, each of said branches having transistor means, each transistor means having a commonly connected drain and a commonly connected gate, the commonly connected gate of one of said transistor means being connected to receive said inverted signal, said transistor means in each of said branches comprising a complementary transistor pair comprising an NMOS transistor and a PMOS transistor, the commonly connected gate of the other one of said transistor means being connected to receive said input signal, whereby at the commonly connected drain of the other transistor means is produced a shifted voltage characterized by a second peak voltage level corresponding to the voltage of said voltage supply, each of said branches of the other branch, whereby current flow from said voltage supply through each of said branches is blocked by either said third transistor or one of the transistors of the complementary transistor pair in the same branch following each voltage transition of said input signal.

6. The improvement of claim 5 further comprising output inverter means, wherein the commonly connected drain of said other one of said transistor means is connected to an input node of said output inverter means.

7. In a digital level shifting circuit having a single voltage supply and input inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inverted signal, the improvement comprising:

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage to said input inverter means, and

latch means energized by said voltage supply and having two branches, each of said branches having transistor means, each transistor means having a commonly connected drain and a commonly connected gate, the commonly connected gate of one of said transistor means being connected to receive said inverted signal, whereby at the commonly connected drain of the other transistor means is produced a shifted voltage characterized by a second peak voltage level corresponding to the voltage of said voltage supply, said voltage generator circuit means comprising;

capacitor means;

a source follower transistor connected between said voltage supply source and said capacitor means, said source follower transistor having a gate connected to receive said input signal and

directional switching means connected between said source follower transistor and said capacitor means for preventing discharge of said capacitor means through said source follower means, whereby said capacitor means compensates for fluctuations in the source voltage of said source follower transistor, said capacitor means being further connected to said input inverter so as to furnish said internally generated supply voltage to said input inverter, said directional switching means comprising a switching transistor having a source and a gate connected together and having a drain connected to said capacitor means, said source follower transistor and said switching transistor having channels which are connected together.

8. A digital level shifting circuit having a single voltage supply, comprising:

input inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inverted signal;

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage different from the voltage of said single voltage supply to said input inverter means, and

latch means energized by said voltage supply and having two branches, each of said branches having a pair of complementary transistors, each pair having commonly connected drains and gates, the commonly connected gate of one of said transistor pairs being connected to receive said inverted signal, whereby at the commonly connected drain of the other transistor pair is produced a shifted voltage characterized by a second peak voltage level corresponding to the level of said voltage supply, the commonly connected gate of the other one of said transistor pairs being connected to receive said input signal.

9. The circuit of claim 8 wherein said voltage generator circuit means comprises:

capacitor means;

a source follower transistor connected between said voltage supply source and said capacitor means, said source follower transistor having a gate connected to receive said input signal; and

digital switching means connected between said source follower transistor and said capacitor means for preventing discharge of said capacitor means through said source follower means, whereby said capacitor means compensates for fluctuations in the source voltage of said source follower transistor, said capacitor means being further connected to said input inverter so as to furnish said internally generated supply voltage to said input inverter.

10. A digital level shifting circuit having a single voltage supply, comprising:

input inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inverted signal;

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage different from the voltage of said single voltage supply to said input inverter means, and

latch means energized by said voltage supply and having two branches, each of said branches having a pair of complementary transistors, each pair having commonly connected drains and gates, the commonly connected gate of one of said transistors pairs being connected to receive said inverted signal, whereby at the commonly connected drain of the other transistor pair is produced a shifted voltage characterized by a second peak voltage level corresponding to the level of said voltage supply, each of said branches of said latch further comprising a third transistor connected in series with the respective complementary transistor pair in the respective branches, the gate of said third transistor in each branch being connected to the commonly connected drain of the complementary transistor pair of the other branche, whereby current flow from said voltage supply through each of said branches is blocked by either said third transistor or one of the transistors of the complementary transistor pair in the same branches following each voltage transition of said input signal.

11. The circuit of claim 10 further comprising output inverter means, wherein the commonly connected drain of said other one of said complementary transistor pairs is connected to an input node of said output inverter means.

12. A digital level shifting circuit having a single voltage supply, comprising:

input inverter means for inverting an input signal characterized by a first peak voltage level to produce therefrom an inverted signal;

voltage generator circuit means energized by said voltage supply for providing an internally generated supply voltage different from the voltage of said single voltage supply to said input inverter means,

latch means energized by said voltage supply and having two branches, each of said branches having a pair of complementary transistors, each pair having commonly connected drains and gates, the commonly connected gate of one of said transistor pairs being connected to receive said inverted signal, whereby at the commonly connected drain of the other transistor pair is produced a shifted voltage characterized by a second peak voltage level corresponding to the level of said voltage supply, said voltage generator circuit means comprising;

capacitor means;

a source follower transistor connected between said voltage supply source and said capacitor means, said source follower transistor having a gate connected to receive said input signal; and

directional switching means connected between said source follower transistor and said capacitor means for preventing discharge of said capacitor means through said source follower means, whereby said capacitor means compensates for fluctuations in the source voltage of said source follower transistor, said capacitor means being further connected to said input inverter so as to furnish said internally generated supply voltage to said input inverter, said directional switching means comprising a switching transistor having a source and a gate connected together and having a drain connected to said capacitor means, said source follower transistor and said switching transistor having channels which are connected together.