Floating gate memory cell and device
First Claim
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1. A nonvolatile storage device comprising:
- a substrate having a trench formed therein;
a first doped region formed on the surface of said trench;
a second doped region formed on the surface of said trench, said second doped region being separated from said first doped region by a channel region said channel region being disposed in said trench;
an insulating layer formed on the surfaces of said trench;
a conductive layer formed on said insulating layer, said conductive layer extending onto the surface of said substrate;
a second insulating layer formed on the surface of said first conductive layer;
a second conductive layer formed on said second insulator layer, said second conductive layer extending onto the surface of said substrate.
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Abstract
One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.
103 Citations
21 Claims
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1. A nonvolatile storage device comprising:
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a substrate having a trench formed therein; a first doped region formed on the surface of said trench; a second doped region formed on the surface of said trench, said second doped region being separated from said first doped region by a channel region said channel region being disposed in said trench; an insulating layer formed on the surfaces of said trench; a conductive layer formed on said insulating layer, said conductive layer extending onto the surface of said substrate; a second insulating layer formed on the surface of said first conductive layer; a second conductive layer formed on said second insulator layer, said second conductive layer extending onto the surface of said substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device comprising:
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a semiconductor structure having a first surface and first and second trenches formed beneath the first surface, said structure including a partition along the surface to separate the trenches, said partition having first and second opposing sides, the first side defining a first wall portion in the first trench and the second side defining a first wall portion in the second trench, each trench further including a bottom surface distinct from the first wall portion and positioned such that each first wall potion extends from the first surface to a bottom surface; first and second bitlines each positioned along a different first wall portion and extending toward a bottom surface; and a memory cell having source and drain electrodes each coupled to a different bitline. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A memory cell formed on a semiconductor structure having a trench formed along first surface thereof, the trench including a bottom surface and first and second wall portions, each wall portion extending from the bottom surface to the first surface, said memory cell comprising:
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a pair of source and drain electrodes each positioned along a different wall portion; a conduction channel region between the source and drain electrodes; a pleat shaped floating gate formed within the trench and electrically isolated from the source and drain electrodes; and a pleat shaped control gate formed within the trench and over said floating gate. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification