Floating gate memory cell and device

• US 4,979,004 A
• Filed: 01/23/1990
• Issued: 12/18/1990
• Est. Priority Date: 01/29/1988
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tigelaar, Howard L., Mitchell, Allan T., Esquivel, Agerico L.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/469,814
• Time in Patent Office: 329 Days
• Field of Search: 357/23.5, 357/55
• US Class Current: 257/316
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Claims

1. A nonvolatile storage device comprising:

a substrate having a trench formed therein;

a first doped region formed on the surface of said trench;

a second doped region formed on the surface of said trench, said second doped region being separated from said first doped region by a channel region said channel region being disposed in said trench;

an insulating layer formed on the surfaces of said trench;

a conductive layer formed on said insulating layer, said conductive layer extending onto the surface of said substrate;

a second insulating layer formed on the surface of said first conductive layer;

a second conductive layer formed on said second insulator layer, said second conductive layer extending onto the surface of said substrate.

2. A device as in claim 1 wherein said substrate comprises crystalline silicon.

3. A device as in claim 1 wherein said first and second conductive layers comprise polycrystalline silicon.

4. A device as in claim 1 wherein said first and second insulating layers comprise silicon dioxide.

5. A device as in claim 1 wherein said second conductive layer extends the width of an array comprising said devices and said first and second doped regions extend the length of said array of said devices.

6. A device as in claim 1 wherein said first conductive layer extends out of said trench onto the surface of said substrate.

7. A device as in claim 1 wherein said second conductive layer extends out of said trench onto the surface of said substrate.

8. A memory device comprising:

a semiconductor structure having a first surface and first and second trenches formed beneath the first surface, said structure including a partition along the surface to separate the trenches, said partition having first and second opposing sides, the first side defining a first wall portion in the first trench and the second side defining a first wall portion in the second trench, each trench further including a bottom surface distinct from the first wall portion and positioned such that each first wall potion extends from the first surface to a bottom surface;

first and second bitlines each positioned along a different first wall portion and extending toward a bottom surface; and

a memory cell having source and drain electrodes each coupled to a different bitline.

9. The device of claim 8 wherein said memory cell includes a conduction channel formed between the first and second bit lines.

10. The device of claim 9 wherein said conduction channel is formed along an upper surface of said partition.

11. The device of claim 9 wherein said memory cell includes a control gate formed over said partition.

12. The device of claim 11 wherein said memory cell further comprises a floating gate positioned between said conduction channel and said control gate.

13. The device of claim 12 wherein said floating gate is formed in a pleat shape about said partition.

14. The device of claim 13 wherein said control gate comprises a pleat shaped portion formed about said floating gate for capacitive coupling.

15. The memory device of claim 8 wherein each bitline is formed over a first wall portion and a bottom surface.

16. A memory cell formed on a semiconductor structure having a trench formed along first surface thereof, the trench including a bottom surface and first and second wall portions, each wall portion extending from the bottom surface to the first surface, said memory cell comprising:

a pair of source and drain electrodes each positioned along a different wall portion;

a conduction channel region between the source and drain electrodes;

a pleat shaped floating gate formed within the trench and electrically isolated from the source and drain electrodes; and

a pleat shaped control gate formed within the trench and over said floating gate.

17. The memory cell of claim 16 wherein said control gate extends out of the trench and along the first surface.

18. The memory cell of claim 16 wherein said floating gate is electrically isolated from the source and drain electrodes by a silicon dioxide layer.

19. The memory cell of claim 16 further comprising a silicon dioxide layer, positioned between said floating gate and said control gate for electrical isolation.

20. The memory cell of claim 16 wherein the source and drain electrodes extend along the trench wall portions toward the bottom surface.

21. The memory cell of claim 16 wherein the source and drain electrodes extend along the trench wall portions to the bottom surface.