Structure and method for improving high speed data rate in a DRAM
First Claim
1. A read/write memory having a set of memory cells in which a memory cell is selected by a first plurality of address signals, a second plurality of address signals, and a control address signal, comprising:
- first decoder means for selecting a first subset of memory cells from said set of memory cells in response to the first plurality of address signals;
second decoder means, coupled to the first decoder means, for selecting a first memory cell and a second memory cell from the first subset of memory cells in response to the second plurality of address signals;
third decoder means, coupled to the second decoder means for selecting between the first memory cell and the second memory cell in response to an internal address signal; and
control means, coupled to the third decoder means, for providing the internal address signal at a logic state which is the same as a logic state of the control address signal when an array toggle signal is in a first logic state and for providing the internal address signal at a logic state which is opposite that of the control address signal when the array toggle signal is in a second logic state.
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Abstract
A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of data required. One of the row addresses provides the final selection between the two bits of data. An array toggle signal available from an extra pin is used to switch the state of the internal signal which corresponds to the one row address signal which makes the final one of two selection. The array toggle signal thus makes it possible to access any of the latched data in a high speed mode in which only the column address is changed to select among the bits of data which are already latched.
59 Citations
19 Claims
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1. A read/write memory having a set of memory cells in which a memory cell is selected by a first plurality of address signals, a second plurality of address signals, and a control address signal, comprising:
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first decoder means for selecting a first subset of memory cells from said set of memory cells in response to the first plurality of address signals; second decoder means, coupled to the first decoder means, for selecting a first memory cell and a second memory cell from the first subset of memory cells in response to the second plurality of address signals; third decoder means, coupled to the second decoder means for selecting between the first memory cell and the second memory cell in response to an internal address signal; and control means, coupled to the third decoder means, for providing the internal address signal at a logic state which is the same as a logic state of the control address signal when an array toggle signal is in a first logic state and for providing the internal address signal at a logic state which is opposite that of the control address signal when the array toggle signal is in a second logic state. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A random access memory having a plurality of memory cells in which a memory cell is selected by a multiplexed address comprised of a first address of n signals comprised of (n-1) row signals and a row control signal, and a second address of n signals received after said first address is received, comprising:
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latch means for latching data from 2 to the (n+1) memory cells in response to the (n-1) row signals from the first address; column decoder means, coupled to the latch means, for selecting data from a first and a second memory cell latched by the latch means in response to the second address of n signals; multiplex means for selecting the first memory cell in response to an internal address signal being in a first logic state and the second memory cell in response to the internal address signal being in a second logic state; and control means for providing the internal address signal at a logic state responsive to that of the row control signal and for reversing the logic state of the internal address signal in response to receiving an array toggle signal. - View Dependent Claims (9, 10, 11)
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12. A random access memory having a set of memory cells, comprising:
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first decoder means for selecting a first subset of memory cells from the set of all memory cells in response to a first signal; second decoder means for selecting a second subset of memory cells from the first subset of memory cells in response to a second signal; third decoder means for selecting a third subset of memory cells from the second subset of memory cells in response to a third signal; and fourth decoder means for selecting a fourth subset of memory cells from the third subset of memory cells in response to a fourth signal or a fifth subset of the memory cells from the third set of memory cells in response to a fifth signal and the fourth signal, said fifth subset disjoint form said fourth subset. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A read/write memory having a set of memory cells in which a memory cell is selected by a first plurality of address signals, a second plurality of address signals, and a control address signal, comprising:
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selecting a first subset of memory cells in response to the first plurality of address signals; selecting a first memory cell and a second memory cell from the first subset of memory cells in response to the second plurality of address signals; selecting between the first memory cell and the second memory cell in response to an internal address signal; and reversing the selection between the first and second memory cell in response to an array toggle signal.
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Specification