Electrically erasable non-volatile semiconductor device

• US 4,979,146 A
• Filed: 01/27/1989
• Issued: 12/18/1990
• Est. Priority Date: 01/28/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Asano, Masamichi, Iwahashi, Hiroshi, Nakagawa, Kaoru, Yokoyama, Sadayuki
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/302,712
• Time in Patent Office: 690 Days
• Field of Search: 365/182, 365/185, 365/218, 357/23.5
• US Class Current: 365/185.14
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

Claims

1. A non-volatile semiconductor memory device comprising:

a row decoder;

a column decoder;

a plurality of row lines;

a plurality of column lines;

a plurality of column selection lines selected by said column decoder, said column selection lines being coupled to said column lines in such a way that a selected column selection line selects the corresponding column line;

a memory cell array including a plurality of non-volatile semiconductor memory cells connected between said row lines and said column lines in a matrix array, each of the memory cells including a floating gate, electrons being excessively discharged from the floating gate so that the floating gate is positively charged when data is erased from the cell in an erasing mode;

means for applying a first voltage having a first voltage level to the column selection lines in a data writing mode; and

means for applying a second voltage having a second voltage level to the row lines in a data writing mode, the second voltage level being lower than the first voltage level.

2. A non-volatile semiconductor memory device according to claim 1, wherein

each of said memory cells further comprises an erasing gate to which a third voltage is applied in the erasing mode.

3. A non-volatile semiconductor memory device comprising:

a row decoder;

a column decoder;

a plurality of row lines;

a plurality of column lines;

a plurality of column selection lines selected by said column decoder, said column selection lines being coupled to said column lines in such a way that a selected column selection line selects the corresponding column line;

a memory cell array including a plurality of non-volatile semiconductor memory cells connected between said row lines and said column lines in a matrix array;

means for applying a first voltage having a first voltage level to the column selection lines in a data writing mode; and

means for applying a second voltage having a second voltage level to the row lines in a data writing mode, the first voltage level being set to a predetermined level higher than a programming voltage of an external power source, the second voltage level being set to a predetermined level lower than that of the programming voltage of the external power source.

4. A non-volatile semiconductor memory device according to claim 3, wherein

each of said memory cells further comprises an erasing gate to which a third voltage is applied in an erasing mode.

5. A non-volatile semiconductor memory device comprising:

a row decoder;

a column decoder;

a plurality of row lines selected by said row decoder;

a plurality of column lines selected by said column decoder;

a memory cell array including a plurality of non-volatile semiconductor memory cells each having a source, drain, control gate, insulating film and floating gate buried in the insulating film, data being stored in the memory cell by injecting charges through the insulating film into the floating gate, said memory cells being arranged in a matrix array, the control gates of the memory cells being connected to the corresponding row lines, respectively and the drains of the memory cells being connected to the column lines, respectively;

means for applying a first level voltage to the column lines in a data writing mode; and

means for applying a second level voltage to the row lines in a data writing mode, the second level voltage being set to have a predetermined level lower than that of the first level voltage.

6. A non-volatile semiconductor memory device according to claim 5, wherein;

and

each of said memory cells further comprising an erasing gate buried in the insulating film, to which a third voltage is applied in an erasing mode.

7. A non-volatile semiconductor memory device comprising:

a plurality of row and column lines;

a memory cell array including a plurality of non-volatile semiconductor memory cells each having a predetermined threshold voltage and a semiconductor structure including a source, drain, control gate, insulating film and floating gate buried in the insulating film, data being stored in the memory cell by injecting charges through the insulating film into the floating gate, said memory cells being arranged in a matrix array, the control gates of the memory cells being connected to the corresponding row lines, respectively, the drains of the memory cells being connected to the column lines, respectively, and the floating gates being maintained at a floating gate potential after data is erased from the memory cells;

means for applying a first voltage to the column lines in a data writing mode so that the drains of the memory cells are maintained at a drain potential, the sum level of the drain potential and the threshold voltage being not smaller than the floating gate potential; and

means for applying a second voltage to the row lines in the data writing mode.

8. A non-volatile semiconductor memory device according to claim 7, wherein;

and

each of said memory cells further comprising an erasing gate buried in the insulating film, to which a third voltage is applied in an erasing mode.

9. A non-volatile semiconductor memory device comprising:

a row decoder;

a column decoder;

a plurality of column lines;

a plurality of column selection lines selected by said column decoder, said column selection lines being coupled to said column lines in such a way that a selected column selection line selects the corresponding column line;

a memory cell array including a plurality of non-volatile semiconductor memory cells connected between said row lines and said column lines in a matrix array;

means for applying a first voltage having a first voltage level to the column selection lines in a data writing mode; and

means for applying a second voltage having a second voltage level to the row lines in a data writing mode, the first voltage level being set to a programming voltage by an external power source, and the second voltage level being set to a predetermined level lower than the first voltage level;

wherein said second voltage applying means includes a converting circuit for converting said programming voltage to the second voltage level, said converting circuit including a first MOS transistor, having a drain connected to the external power source, a source connected to the second voltage level, a second MOS transistor having a drain connected to the external power source and a gate of the first MOS transistor, a gate connected to the second voltage level, resistor means connected in series between the external power source and ground, and a source of the second MOS transistor connected to a connecting node of the resistor means.

10. A non-volatile semiconductor memory device comprising:

a row decoder;

a column decoder;

a plurality of row lines;

a plurality of column lines;

a plurality of column selection lines selected by said column decoder, said column selection lines being coupled to said column lines in such a way that a selected column selection line selects the corresponding column line;

a memory cell array including a plurality of non-volatile semiconductor memory cells connected between said row lines and said column lines in a matrix array;

means for applying a first voltage level to the column selection lines in a data writing mode; and

means for applyikng a second voltage level to the row lines in a data writing mode, the first voltage level being set to a predetermined level higher than a programming voltage of an external power source, the second voltage level being set to a predetermined level lower than that of the programming voltage of the external power source;

wherein said second voltage applying means includes a converting circuit for converting the programming voltage of the external power source to the second voltage, said converting circuit including a MOS transistor having a drain connected to the external power source, a source connected to the second voltage level, resistor means connected in series between the external power source and gorund, and a gate of the MOS transistor connected to a connecting node of the resistor means.