Increasing options in mapping ROM in computer memory space

• US 4,979,148 A
• Filed: 12/09/1988
• Issued: 12/18/1990
• Est. Priority Date: 12/09/1988
• Status: Expired due to Fees

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bush, Gregory F., Morel, Jeanne E., Keener, Don S., Voorhees, Richard W.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/281,612
• Time in Patent Office: 739 Days
• Field of Search: 365/230.01, 365/230.03, 364/200 MS File, 364/900 MS File
• US Class Current: 365/230.01
• CPC Class Codes: G06F 12/0661 and decentralised selection

Abstract

In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its outputs to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

Claims

1. A device comprising a component of a personal computer system, said component including read only memory;

said read only memory including two addressable fields,

a first addressable field storing read only instruction codes for said component in a given sequential order, said given sequential order comprising a first group of instruction codes followed by a second group of instruction codes, and

a second addressable field storing identical instruction codes in a different order, said different order comprising said second group of instruction codes followed by said first group of instruction codes.

2. The device as recited in claim 1 wherein said component is a feature card adapted for plug insertion into the personal computer system.

3. A feature card as recited in claim 2 wherein said first group of instruction codes in said second addressable field is located relative to a beginning of said second addressable field in a position identical to a position of said second group of instruction codes in said first addressable field relative to a beginning of said first addressable field.

4. A method of initializing and addressing a read only memory of a personal computer system which includes read only memory instruction codes for insertion into a programmable region of a read only memory space of said personal computer system, said method comprising the steps of:

(a) storing said read only instruction codes in two distinct fields of said read only memory,

(i) a first field storing read only instruction codes in a given sequential order, said given sequential order comprising a first group of instruction codes followed by a second group of instruction codes, and

(ii) a second addressable field storing identical instruction codes in a different order, said different order comprising said second group of instruction codes followed by said first group of instruction codes,

(b) determining whether said first or said second field is to be used by determining whether read only memory space is available for said first field,

(i) if read only memory space is available for said first field then writing a first code to a programmable register and if read only memory space is not available for said first field then writing a different, second, code to said programmable register, and

(c) providing address modification logic responsive to address input signals and to a code stored in said programmable register for developing addressing signals for read only memory.

5. A method as recited in claim 4 which includes the further steps of:

modifying address input signals in said address modification logic to produce said addressing signals only in the event said second code is stored in said programmable register.

6. A method of locating feature card resident read only code into read only memory space of a computer system in which said feature card is attached, said method comprising the steps of:

(a) providing said feature card resident read only code in two different fields in feature card resident read only memory,

(i) a first field storing read only code in a given sequential order, said given sequential order comprising a first group of codes followed by a second group of codes, and

(ii) a second field storing identical codes in a different order, said different order comprising said second group of codes followed by said first group of codes,

(b) storing a read only memory segment indicator identifying a read only memory segment for said feature card resident read only code, said segment indicator having either a first or a second characteristic,

(c) in the event said segment indicator has said first characteristic, then addressing said first field and in the event said segment indicator has said second characteristic, then addressing said second field.