Method and apparatus for performing format conversion between bit streams

• US 4,979,169 A
• Filed: 02/14/1989
• Issued: 12/18/1990
• Est. Priority Date: 02/14/1989
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Nobile, Daniel A., Almond, Gary R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/310,454
• Time in Patent Office: 672 Days
• Field of Search: 370/99, 370/84, 370/79, 370/82, 370/85.1, 370/100.1, 370/105.1
• US Class Current: 370/466
• CPC Class Codes: G05B 2219/31174 Load, use different protocols, formats, emulators for different systems
• CPC Class Codes: H04J 3/1635 Format conversion, e.g. CEPT/US

Abstract

Methods and apparatus are set forth that perform Format Conversion between bit streams which embed sub-rate circuit data according to different protocols. The invention (1) locates and extracts the sub-rate circuit data embedded, in an input serial bit stream, in accordance with a first predefined protocol (2) aligns the data in a buffer, and (3) creates an output bit stream in which the extracted circuit data is reformatted and inserted in accordance with a second predefined protocol. A programmable bit map driven format conversion module operates the data aligned in the aforementioned buffer. The conversion process is bidirectional and, in one embodiment of the invention, facilitates conversion between a single stage time division multiplexed data format and a two stage time division multiplexed format (e.g. X.50 and I.463) by utilizing the aforesaid bit map driven format conversion technique. More generally, the invention permits conversion between any two predefined protocols, permits great flexibility in network system configuration and permits multiple channels of different format or frame alignments to be converted simultaneously.

Claims

1. Apparatus, for use in a digital communication system that carries data in a plurality of sub-rate data formats, for converting a first serial bit stream, with data embedded therein in accordance with a first predefined sub-rate data format, into a second bit stream, with data embedded therein in accordance with a second predefined sub-rate data format, comprising:

(a) means for locating and extracting the sub-rate data, formatted in accordance with said first predefined sub-rate data format, embedded in said first serial bit stream;

(b) means, coupled to said means for locating and extracting, for aligning and storing said extracted data; and

(c) conversion means, coupled to said means for aligning and storing, for construction said second serial bit stream from the stored extracted data utilizing a bit map designed to organize said second serial bit stream in accordance with said second predefined sub-rate data format.

2. Apparatus as set forth in claim 1 which may be used to convert between data formatted in a single stage time division multiplexed format and data formatted in a two stage time division multiplexed format.

3. Apparatus as set forth in claim 1 which may be used to convert sub-rate circuit data embedded in said first serial bit stream, formatted in accordance with CCITT X.50 recommendations, to a serial bit stream containing sub-rate circuit data formatted in accordance with CCITT I.463 recommendations.

4. Apparatus as set forth in claim 1 which may be used to convert sub-rate circuit data embedded in said first serial bit stream, formatted in accordance with CCITT I.463 recommendations, to a serial bit stream containing sub-rate circuit data formatted in accordance with CCITT X.50 recommendations.

5. Apparatus as set forth in claim 1 wherein multiple channels of different formats can be aligned and converted simultaneously.

6. Apparatus as set forth in claim 1 wherein said means for locating and extracting further comprises frame synchronization detection means.

7. Apparatus as set forth in claim 6 wherein said means for locating and extracting further comprises frame index generator means.

8. Apparatus as set forth in claim 6 wherein said means for locating and extracting further comprises circuit index generator means.

9. Apparatus as set forth in claim 1 wherein said conversion means is programmable.

10. Apparatus, in a digital communication system including a timer for providing frame synchronization and clock signals, for converting a first serial bit stream, with sub-rate circuit data formatted according to a first predetermined protocol embedded therein, into a second serial bit stream, with said sub-rate circuit data formatted in accordance with a second predetermined protocol embedded therein, comprising:

(a) means, coupled to said timer, for generating a current address signal to indicate channel and frame number for the information being input by way of said first serial bit stream;

(b) synchronization and index generation means, for detecting the starting postion of frames and multiframes in order to create an address offset into an aligned data memory used to collect and store sub-rate circuit information;

(c) aligned data memory means coupled to said synchronization and index generator means, for aligning and storing sub-rate circuit data therein;

(d) format conversion module means, including a predefined bit map driven by the aforesaid channel and frame number, for assembling a frame of reformatted sub-rate circuit information, reformatted according to said second predefined protocol, and for embedding said frame of reformatted information in said second bit stream; and

(e) means for outputting said second serial bit stream with the reformatted sub-rate circuit data embedded therein.

11. Apparatus as set forth in claim 10 wherein said synchronization and index generator means includes means for generating a frame index.

12. Apparatus as set forth in claim 10 wherein said synchronization and index generator means includes means for generating a circuit index.

13. Apparatus as set forth in claim 10 wherein said format conversion module is programmable.

14. A method, for use in a digital communication system that carries data in a plurality of sub-rate data formats, for converting a first serial bit stream, with data embedded therein in accordance with a first predefined sub-rate data format, into a second bit stream, with data embedded therein in accordance with a second predefined sub-rate data format, comprising the steps of:

(a) locating the sub-rate data formatted in accordance with said predefined sub-rate data format, embedded in said first serial bit stream;

(b) extracting the formatted sub-rate data so located and storing same in an aligned fashion in a storage means; and

(c) constructing said serial bit stream from the stored aligned data utilizing a bit map designed to organize said second serial bit stream in accordance with said second predefined sub-rate data format.