Transceiver employing direct sequence spread spectrum techniques

• US 4,979,183 A
• Filed: 03/23/1989
• Issued: 12/18/1990
• Est. Priority Date: 03/23/1989
• Status: Expired due to Term

• Current Assignee: Echelon Systems Corp.
• Original Assignee: Echelon Systems Corp.
• Inventors: Cowart, Brooks
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US07/328,058
• Time in Patent Office: 635 Days
• Field of Search: 375/1
• US Class Current: 375/142
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/70757 with increased resolution, i.e. higher than half a chip H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates

Abstract

A transceiver for transmitting and receiving digital data is disclosed. The transceiver employs direct sequence spread spectrum communications techniques for reducing interference among multiple users in a communications network environment. Each transceiver has a transmitter for locking a digital bit stream to a predetermined spread spectrum chip sequence and carrier signal. Frequency of the carrier signal and the chip sequence. Both the carrier signal, the chip sequence and the bit stream rate are derived from an integrally related to an accurate reference frequency to facilitate rapid acquisition and decoding of the signal by another transceiver. The transceiver also has a receiver portion for acquiring and decoding a transmitted and direct sequence spread spectrum signal to recover the digital bit stream using the spread spectrum chip sequence and carrier signal.

Claims

1. An integrated circuit for transmitting and receiving digital information across various communications media comprising:

a frequency means for generating a reference frequency;

transmitter means for locking a digital bit stream, a carrier signal and a pseudoniose chip sequence to produce a direct sequence spread spectrum signal for transmission to another integrated circuit;

receiver means for acquiring and decoding a previously transmitted direct sequence spread spectrum signal using a local carrier signal and a local pseudonoise chip sequence to recover said digital bit stream; and

wherein said carrier signal and said pseudonoise chip sequence are substantially identical to said local carrier signal and said local pseudonoise chip sequence, respectively, and each are derived from, and integral multiples of said reference frequency.

2. The integrated circuit of claim 1 wherein said preference frequency means comprises at least one crystal resonator circuit.

3. The integrated circuit of claim 2 wherein said receiver means further comprises an integrate and dump filter for demodulating said carrier signal from said previously transmitted direct sequence spread spectrum signal.

4. The integrated circuit of claim 3 further comprising a correlator means for correlating said demodulated direct sequence spectrum signal with all possible code positions of said local pseudonoise chip sequence to recover said digital bit stream.

5. The integrated circuit of claim 4 further comprising phase adjustment means for detecting and correcting phase errors between said direct sequence spread spectrum signal and said local carrier signal.

6. A transceiver for transmitting and receiving digital data comprising:

a resonator means for producing a reference frequency;

a transmitter means for encoding a digital bit stream to a direct sequence spread spectrum signal and for transmitting said direct sequence spread spectrum signal to another transceiver, said transmitter means locking said digital bit stream to a predetermined spread spectrum chip sequence and to a carrier signal, the frequency of said carrier signal, said chip sequence and said bit stream being integral multiples of said reference frequency to facilitate acquisition and decoding of said direct sequence spread spectrum signal by another transceiver; and

a receiver means for rapidly acquiring and decoding a transmitted direct sequence spread spectrum signal to recover said digital bit stream using said predetermined spread spectrum chip sequence and said carrier signal.

7. The transceiver of claim 6 wherein said transmitter means comprises:

a carrier generator for receiving said reference frequency and producing said carrier signal therefrom;

a pseudonoise generator means for receiving said reference frequency and producing said spread spectrum chip sequence therefrom;

a direct sequence/binary phase shift keyed modulator for locking said carrier signal, said spread spectrum chip sequence and said digital bit stream to produce said direct sequence spread spectrum signal; and

wherein

said receiver means comprises;

an integrate and dump filter for acquiring and demodulating said carrier signal from said transmitted direct sequence spread spectrum signal;

a correlator for synchronizing said demodulated direct sequence spread spectrum signal to said predetermined spread spectrum chip sequence;

data recovery means coupled to said correlator for decoding said digital bit stream from said synchronized demodulized direct sequence spread spectrum signal, said data recovery means including correction means coupled to said carrier generator for reducing phase error between said transmitted direct sequence spread spectrum signal and said carrier signal.

8. The transceiver of claim 7 wherein said resonator means comprises a crystal resonator circuit providing a reference frequency for frequency synchronization of various transceivers.

9. The transceiver of claim 8 wherein said transmitter means further comprises a data storage means for storing said digital bit stream and outputting the individual bits of said bit stream to said modulator;

and

a power amplifier for transmitting said direct sequence spread spectrum signal across a transmission media.

10. The transceiver of claim 9 wherein said receiver means further comprises a limiting amplifier for filtering noise associated with said transmitted direct sequence spread spectrum signal prior to being input into said integrate and dump filter.

11. The transceiver of claim 10 wherein said correlator comprises a linear shift register having a plurality of bits equal to the number of chips in said spread spectrum chip sequence.

12. The transceiver of claim 11 wherein the frequency of said carrier signal is between 2 and 10 times the chip rate of said spread spectrum chip sequence.

13. In a communications network having sensing, communications, and control and which contains a plurality of intelligent neuron cells, a transceiver for transmitting and receiving digital data between said cells, said transceiver comprising:

a crystal resonator providing a predetermined reference frequency;

a transmitter including;

a frequency divider for deriving a carrier signal from said predetermined reference frequency such that said predetermined frequency is an integer multiple of said carrier signal;

a pseudonoise generator means for deriving a chip sequence from said predetermined reference frequency such that said chip sequence is an integer multiple of said carrier signal;

locking means for locking the bits of said digital data to said chip sequence and said carrier signal to produce a direct sequence spread spectrum signal for transmission to another transceiver;

a receiver including

a first circuit means for filtering the noise associated with a received direct sequence spread spectrum signal from another transceiver and for amplifying said received direct sequence spread spectrum signal, said first circuit means producing a conditioned direct sequence spread spectrum signal;

an integrate and dump filter for receiving and demodulating said conditioned direct sequence spread spectrum signal using said carrier signal and said chip sequence.

14. The transceiver of claim 13 wherein said integrate and dump filter includes an inphase detector means and a quadrature detector means each clocked from said frequency divider at a rate approximately equal to the frequency of said carrier signal but with said quadrature detector means being offset in phase from said inphase detector means by a certain amount so as to insure that either said inphase detector means or said quadrature detector means will be substantially in phase with said conditioned direct sequence spread spectrum signal, thereby facilitating rapid capture and demodulation of said direct sequence spread spectrum signal.

15. The transceiver of claim 14 further comprises a static correlator means for producing an output corresponding to the correlation of said demodulated direct sequence spread spectrum signal and said predetermined chip sequence.

16. The transceiver of claim 15 wherein said receiver further comprises a data recovery circuit coupled to said output of said static correlator means, said circuit recovering said digital data from said output and providing adjustment signals to said frequency divider and said pseudonoise generator means so as to compensate for differences in phase or frequency between said transmitted direct sequence spread spectrum signal and said frequency divider and also for synchronizing said pseudonoise sequence generator means to said demodulated direct sequence spread spectrum signal.