Dual triggered edge-sensitive asynchrounous flip-flop

• US 4,980,577 A
• Filed: 05/23/1989
• Issued: 12/25/1990
• Est. Priority Date: 06/18/1987
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Baxter, Michael A.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Duong, Tai V.
• Application Number:
  US07/356,572
• Time in Patent Office: 581 Days
• Field of Search: 307/272.1, 307/272.2, 307/291, 307/292, 307/471, 307/480, 307/514, 307/516, 307/525-528, 307/238.6, 307/465, 307/269, 307/518, 307/445, 307/443, 328/133, 328/134, 328/206
• US Class Current: 327/198
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

An architecture for bistable circuits with minimized sensitivity to metastability events and with improved operation in signal timing, arbitration, and protocol applications. Conventional edge-triggered flip-flops require input signals to remain present during certain set-up and/or hold time intervals on an input line "data path" for sampling at an instant determined by a separate synchronization input signal. In contrast, the present invention uses two edge-sensitive input lines which are triggered essentially independently without either being synchronized by or depending upon the other. The flip-flops also have twin, independently operable, level sensitive and selected priority PRESET and CLEAR input lines. The active edge or level polarity is programmable for each input line. Alternate embodiments for complementary classes of asynchronous timing perform specific bistable functions, such as set-reset, or toggle.

Claims

1. A flip-flop circuit comprising:

a first flip-flop having four input terminals for receiving input signals thereat;

a second flip-flop having at least three input terminals for receiving input signals thereat;

means for providing a first input signal to a first input terminal of the first flip-flop;

means for providing a second input signal to a first input terminal of the second flip-flop;

a priority circuit for determining priority between input signals and for receiving at first and second input terminals thereof, respectively a third input signal and a fourth input signal, and also having a first and a second output terminal for issuing output signals;

wherein the first output terminal of the priority circuit is connected to a third input terminal of the second flip-flop and wherein the second output terminal of the priority circuit is connected to a third input terminal of the first flip-flop;

wherein the third input signal is provided to a fourth input terminal of the first flip-flop;

an output logic circuit having two input terminals for receiving signals thereat and one output terminal for issuing an output signal, wherein the output logic circuit logically combines the signals received at its input terminals;

wherein a first output terminal of the first flip-flop is connected to a first input terminal of the output logic circuit, and wherein a first output terminal of the second flip-flop is connected to a second input terminal of the output logic circuit; and

wherein a second output terminal of the first flip-flop is connected to a second input terminal of the first flip-flop and wherein a second output terminal of the second flip-flop is connected to a second input terminal of the second flip-flop.

2. The device of claim 1, wherein the priority circuit includes a NAND gate and a NOR gate, and wherein the NAND gate receives the third and fourth input signals at its input terminals and has an output terminal connected to the third input terminal of the first flip-flop, and wherein the NOR gate receives the third and fourth input signals at its input terminals and has its output terminal connected to the third input terminal of the second flip-flop.

3. The device of claim 1, wherein the output logic circuit includes a XOR gate having two input terminals respectively connected to the first output terminal of the first flip-flop and to the first output terminal of the second flip-flop and wherein the output terminal of the XOR gate is the output terminal of the circuit.

4. The device of claim 1, wherein both the first flip-flop and the second flip-flop are D type flip-flops.

5. A bistable dual triggered 2T flip-flop circuit comprising:

a logic circuit having first, second, third and fourth input terminals to receive first, second third and fourth input signals thereat and having first and second output terminals to issue first and second output signals thereat;

arbitration means for receiving the third input signal and the fourth input signal and, when these two signals are driven substantially simultaneously to their active states, for arbitrating between the third and fourth input signals and determining which of these two signals shall preempt the other of these two signals in determining the first output signal and the second output signal thereby providing arbitration outputs;

first and second sequential logic input stages, operating substantially in parallel, with each stage responsive only to a different one of the first input signal and the second input signal, where the first logic input stage receives the first input signal, the third input signal and one of the arbitration outputs and produces a first intermediate signal that cannot cause a metastable state in the circuit, and where the second logic input stage receives the second input signal and another one of the arbitration outputs and produces a second intermediate signal that cannot cause a metastable state in the circuit;

a logic output stage that receives the first intermediate signal and the second intermediate signal, and produces an output signal as a logical combination thereof;

wherein an inversion of the first intermediate signal is provided as an input signal to the first logic input stage, and an inversion of the second intermediate signal is provided as an input signal to the second logic input stage.

6. A circuit comprising:

a first logic circuit having three input terminals for receiving input signals thereat and having at least one output terminal and wherein a signal is provided at the output terminal that cannot cause a metastable state in the circuit;

a second logic circuit having three input terminals for receiving input signals thereat and having one output terminal and wherein a signal is provided at the output terminal that cannot cause a metastable state in the circuit;

means for providing a first input signal to a first input terminal of the first logic circuit;

means for providing a second input signal to a first input terminal of the second logic circuit;

a priority circuit for determining priority between input signals and having two input terminals for receiving input signals thereat and having one output terminal, and wherein a third input signal is provided to a first input terminal of the priority circuit;

an output logic circuit having four input terminals for receiving input signals thereat and having two output terminals for providing output signals, wherein the output logic circuit produces the output signals according to the phases of each of the signals input thereto without causing any metastability in the circuit;

means for providing a fourth input signal to a second input terminal of the priority circuit, and to a second input terminal of the second logic circuit, and to a fourth input terminal of the output logic circuit;

wherein the output terminal of the first logic circuit is connected to a second input terminal of the output logic circuit, and wherein the output terminal of the second logic circuit is connected to a third input terminal of the output logic circuit; and

wherein a first output terminal of the output logic circuit is connected to a third input terminal of the first logic circuit and wherein a second input terminal of the output circuit is connected to a third input terminal of the second logic circuit.

7. The device of claim 6, wherein the priority circuits include a NAND gate having two input terminals connected respectively for receiving the third input signal and the fourth input signal, and having its output terminal connected to the second input terminal of the first logic circuit and to the first input terminal of the output logic circuit.

8. The device of claim 6, wherein a polarity of the signal at the first output terminal of the output logic circuit is inverse to a polarity of the signal at the second output terminal of the output logic circuit.

9. A bistable dual triggered RS flip-flop circuit comprising:

a logic circuit having first, second, third and fourth input terminals to receive first, second, third and fourth input signals thereat and having first and second output terminals to issue first and second output signals thereat;

arbitration means for receiving the third input signal and the fourth input signal and, when these two signals are driven substantially simultaneously to their active states, for arbitrating between the third and fourth input signals and determining which of these two signals shall preempt the other of these two signals in determining the first output signal and the second output signal;

first and second sequential logic input stages, operating substantially in parallel, with each stage responsive only to a different one of the first input signal and the second input signal, where the first logic input stage receives the first input signal, and produces a first intermediate signal that cannot cause a metastable state in the circuit; and

where the second logic input stage receives the second input signal and the third input signal and produces a second intermediate signal that cannot cause a metastable state in the circuit;

a logic output stage that receives the third input signal, the product of the third input signal and the fourth input signal, the first intermediate signal and the second intermediate signal, and produces an output signal according to the phases of the first input signal, the second input signal, the third input signal and the fourth input signal without causing any metastability in the circuit;

first feedback means for providing the output signal as an input signal to the first logic input stage; and

second feedback means for providing an inversion of the output signal as an input to the second input stage.

10. A bistable flip-flop circuit comprising:

circuit means having first, second, third and fourth input terminals adapted to receive first, second, third and fourth input signals, respectively, and having first and second output terminals to issue output signals thereat, where receipt of an active fourth input signal preempts the remainder of the circuit except for the third input signal, and determines the first and second output signals, and receipt of an active third input signal preempts the fourth input signal and the remainder of the circuit and determine the first and second output signals;

first, second, third, fourth, fifth, sixth and seven NAND gates, each having an output terminal for issue of a NAND gate output signal thereat, with the first, second third, fourth, fifth and sixth NAND gates each having three input terminals, and with the seventh NAND gate having two input terminals, with the first, fifth and seventh NAND gates each receiving the third input signal, with the second and third NAND gates each receiving the first input signal, with the first NAND gate receiving the second NAND gate output signal and receiving the fourth NAND gate output signal, with the second NAND gate receiving the first NAND gate output signal and receiving the seventh NAND gate output signal, with the third NAND gate receiving the second NAND gate output signal and receiving the fourth NAND gate output signal, with the fourth NAND gate receiving the third NAND gate output signal and receiving the sixth NAND gate output signal and receiving the seventh NAND output signal, with the fifth NAND gate receiving the second NAND gate output signal and receiving the sixth NAND gate output signal, with the sixth NAND gate receiving the fifth NAND gate output signal and receiving the third NAND gate output signal and receiving the seventh NAND gate output signal, and with the seventh NAND gate receiving the binary complement of the fourth input signal;

a first NOR gate having two input terminals and an output terminal to issue an output signal thereof, with the NOR gate receiving the third and fourth input signals at its input terminals;

eighth, ninth, tenth, eleventh, twelfth and thirteenth NAND gate, each having an output terminal to issue an output terminal to issue an output signal thereat, with the ninth, tenth, eleventh, thirteenth NAND gates each having three input terminals and with the eighth and twelfth NAND gates each having two input terminals, with the ninth, eleventh and thirteenth NAND gates each receiving the output signal from the first NOR gate, with the eighth NAND gate receiving the ninth NAND gate output signal and receiving the eleventh NAND gate output signal, with the ninth and tenth NAND gates each receiving the second input signal, with the ninth NAND gate receiving the eighth NAND gate output signal, with the tenth NAND gate receiving the ninth NAND gate output signal and receiving the eleventh NAND output signal, with the eleventh NAND gate receiving the thirteenth NAND gate output signal, with the twelfth NAND gate receiving the ninth NAND gate output signal and receiving the thirteenth NAND gate output signal, and with the thirteenth NAND gate receiving the twelfth NAND gate output signal and receiving the tenth NAND gate output signal;

first, second, third and fourth AND gates, each having two input terminals and each having an output terminal to issue an output signal thereat, with the first AND gate receiving the fifth NAND gate output signal and receiving the thirteenth NAND gate output signal, with the second AND gate receiving the sixth NAND gate output signal and receiving the twelfth NAND gate output signal, with the third NAND gate receiving the sixth NAND gate output signal and receiving the thirteenth AND gate output signal, and with the fourth AND gate receiving the fifth NAND gate output signal and receiving the twelfth NAND gate output signal; and

a first NOR gate and an OR gate, each gate having two input terminals and an output terminal to issue output signals thereat, with the first NOR gate receiving the second AND gate output signal and receiving the third AND gate output signal, with the OR gate receiving the fourth AND gate output signal and receiving the fifth AND gate output signal, where the first NOR gate and the OR gate issue first and second output signals, respectively, that are binary complements of one another, where receipt of an active signal at the third input terminal determines the first and second output signals of the circuit irrespective of any signals simultaneously or subsequently received at the first input terminal, the second input terminal or the fourth input terminal, and where receipt of an active signal at the fourth input terminal determines the first and second output signals of the circuit irrespective of any signals simultaneously or subsequently received at the first input terminal or the second input terminal.

11. A bistable flip-flop circuit comprising:

circuit means having first, second, third and fourth input terminals adapted to receive first, second, third and fourth input signals, respectively, and having first and second output terminals to issue output signals thereat, where receipt of an active fourth input signal preempts the remainder of the circuit, except for the third input signal, and determines the first and second output signals, and receipt of an active third input signal preempts the fourth input signal and the remainder of the circuit and determines the first and second output signals;

first, second, third, fourth, fifth, sixth, seventh, and eighth and ninth NAND gates, each having an output terminal for issue of a NAND gate output signal thereat, with the first, fourth, fifth, sixth and ninth NAND gates each having two input terminals and with the second, third, seventh and eighth NAND gates each having three input terminals;

first and second signal inverters, each having an input terminal to receive and input signal and having an output terminal to issue an output signal thereat;

with the first and fifth NAND gates each receiving the first input signal, with the fourth and sixth NAND gates each receiving the second input signal, with the third, seventh and ninth NAND gates each receiving the third input signal, and with the ninth NAND gate receiving the fourth input signal;

with the first NAND gate receiving the second NAND gate output signal, with the second NAND gate receiving the first NAND gate output signal and receiving the ninth NAND gate output signal and receiving the first inverter output signal;

with the third NAND gate receiving the fourth NAND gate output signal and receiving the second inverter output signal, with the fourth NAND gate receiving the third NAND gate output signal;

with the fifth NAND gate receiving the first NAND gate output signal, with the sixth NAND gate receiving the fourth NAND gate output signal;

with the seventh NAND gate receiving the fifth NAND gate output signal and receiving the eighth NAND gate output signal, with the eighth NAND gate receiving the sixth NAND gate output signal and receiving the seventh NAND gate output signal and receiving the ninth NAND gate output signal; and

with the first inverter receiving the seventh NAND gate output signal, and with the second inverter receiving the eighth NAND gate output signal, where the output signals of the first and second inverters serve as the first and second output signals of the circuit.