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Dual triggered edge-sensitive asynchrounous flip-flop

  • US 4,980,577 A
  • Filed: 05/23/1989
  • Issued: 12/25/1990
  • Est. Priority Date: 06/18/1987
  • Status: Expired due to Term
First Claim
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1. A flip-flop circuit comprising:

  • a first flip-flop having four input terminals for receiving input signals thereat;

    a second flip-flop having at least three input terminals for receiving input signals thereat;

    means for providing a first input signal to a first input terminal of the first flip-flop;

    means for providing a second input signal to a first input terminal of the second flip-flop;

    a priority circuit for determining priority between input signals and for receiving at first and second input terminals thereof, respectively a third input signal and a fourth input signal, and also having a first and a second output terminal for issuing output signals;

    wherein the first output terminal of the priority circuit is connected to a third input terminal of the second flip-flop and wherein the second output terminal of the priority circuit is connected to a third input terminal of the first flip-flop;

    wherein the third input signal is provided to a fourth input terminal of the first flip-flop;

    an output logic circuit having two input terminals for receiving signals thereat and one output terminal for issuing an output signal, wherein the output logic circuit logically combines the signals received at its input terminals;

    wherein a first output terminal of the first flip-flop is connected to a first input terminal of the output logic circuit, and wherein a first output terminal of the second flip-flop is connected to a second input terminal of the output logic circuit; and

    wherein a second output terminal of the first flip-flop is connected to a second input terminal of the first flip-flop and wherein a second output terminal of the second flip-flop is connected to a second input terminal of the second flip-flop.

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