Sequential prefetching with deconfirmation

• US 4,980,823 A
• Filed: 01/05/1990
• Issued: 12/25/1990
• Est. Priority Date: 06/22/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Lishing
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/463,867
• Time in Patent Office: 354 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/136
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/6024 History based prefetching
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bit in an S-vector, which is called the S-bit for the line. When the S-bit is on, sequentiality is predicted meaning that the sequentially next line is regarded as a good candidate for prefetching, if that line is not already in the cache memory. The key to the operation of the memory management method is the manipulation (turning on and off) the S-bits.

Claims

1. A computer performed method for prefetching sequential lines from main memory into a processor cache memory of a computer, said cache memory including an S-vector comprising an S-bit associated with lines in main memory, said S-b being indicative of whether a succeeding line is likely to be accessed when a line in memory corresponding to said S-bit is accessed, the S-bits of said S-vector initially being set on, said method comprising the steps of:

testing an access to the cache memory to determine if an accessed line is in the cache memory, and if it is, accessing the line;

otherwise, fetching the accessed line from main memory;

testing the accessed line in the cache memory to determine if it is in a Most-Recently-Used position, and if it is not, making the line the Most-Recently Used;

testing said S-bit for the accessed line to determine if it is on, and if it is, testing to determine if a sequential next line is in the cache memory; and

if said sequential next line is not in the cache memory, prefetching the sequential next line into the cache memory as a new line and keeping the new line at a Least-Recently-Used position in the cache memory.

2. The method of prefetching lines into a cache memory as recited in claim 1 wherein an R-bit is associated with each cache line entry, said R-bit being indicative of whether the current line at entry has actually been accessed, said R-bit initially being set on, said method further comprising the step of:

when said sequential next line is prefetched into the cache memory as a new line, turning said R-bit off at said new line.

3. The method of prefetching lines into a cache memory as recited in claim 2 further comprising the step of turning said R-bit on when accessing a line in the cache memory in a non-Most-Recently-Used position.

4. The method of prefetching lines into a cache memory as recited in claim 3 wherein when a line is replaced from the cache memory, further comprising the steps of testing the R-bit to determine if it is on, and if it is not, turning the S-bit for a next preceding line in the cache memory off.

5. The method of prefetching lines into a cache memory as recited in claim 3 wherein when there is a miss on a line on an access to the cache memory, further comprising the steps of testing to determine if a preceding line is in the cache memory, and if it is, turning the S-bit for the preceding line on.

6. The method of prefetching lines into a cache memory as recited in claim 3 wherein when there is a miss on a line on an access to the cache memory, further comprising the steps of testing a preceding line in the cache memory to determine if it has been accessed lately, and if it has, turning the S-bit on for the preceding line.

7. The method of prefetching lines into a cache memory as recited in claim 2 wherein when said new line is prefetched into the cache memory, performing the following additional steps of testing the R-bit for the new line to determine if it is on, and if it is not, turning said S-bit on for the preceding line and turning said R-bit on for the new line.

8. The method of prefetching lines into a cache memory as recited in claim 7 wherein when said line is prefetched into the cache memory, further comprising the step of turning the S-bit off for the preceding line and the R-bit off at the new entry of the cache memory.

9. The method of prefetching lines into a cache memory as recited in claim 1 wherein when said new line is prefetched into the cache memory, performing the following additional steps of testing to determine if the line is in the Least-Recently-Used position, and if it is, turning the S-bit for the line on.

10. The method of prefetching lines into a cache memory as recited in claim 9 wherein when said next sequential line is prefetched into the cache memory, preforming the additional step of turning the S-bit off for that line.

11. In a computer system having a processor, a memory for storing a plurality of storage lines for use by said processor, and a cache for holding storage lines received from said memory for use by said processor, prefetching apparatus comprising:

means for storing a plurality of S-bits,

each storage line in said memory corresponding with one of said S-bits,

each S-bit having first and second alternate states, said first alternate state indicating that when a corresponding storage line is accessed by said processor, the next sequential storage line also is likely to be accessed soon by said processor, and

said second alternate state indicating that when a corresponding storage line is accessed by said processor, the next sequential storage line is not likely to be accessed soon by said processor;

means for determining whether the S-bit corresponding with a storage line accessed by said processor is in said first state;

means responsive to said S-bit state determining means for prefetching into said cache the next sequential storage line when said S-bit is in said first state unless said next sequential storage line is already in said cache;

deconfirmation means for determining whether said prefetched next sequential storage line was accessed by said processor before it was replaced in said cache; and

means responsive to said deconfirmation means for setting the state of the S-bit corresponding with the storage line preceding said prefetched next sequential storage line to said second state in the event that said deconfirmation means determines that said prefetched next sequential storage line was not accessed by said processor before it was replaced in said cache.

12. Prefetching apparatus as defined in claim 11 wherein all S-bits are initially set to said first state.

13. Prefetching apparatus as defined in claim 11 wherein all S-bits are initially set to said second state.

14. Prefetching apparatus as defined in claim 11 and further comprising means for determining upon a cache miss, whether the next preceding sequential storage line is stored in said cache, and if said next preceeding sequential storage line is stored in said cache, setting the S-bit corresponding to said next preceeding sequential storage line to said first state.

15. Prefetching apparatus as defined in claim 11 wherein each storage line in said memory corresponds uniquely with an individual S-bit.

16. Prefetching apparatus as defined in claim 11 wherein each S-bit corresponds with more than one storage line in said memory.

17. Prefetching apparatus as defined in claim 11 wherein the state of the S-bit corresponding with a storage line accessed by said processor is determined by said S-bit state determining means when said storage line is fetched into said cache in response to a cache miss.

18. Prefetching apparatus as defined in claim 11 wherein the state of the S-bit corresponding with a storage line accessed by said processor is determined by said S-bit state determining means what said processor accesses a new storage line different from the storage line previously accessed by said processor.

19. Prefetching apparatus as defined in claim 11 wherein prefetched storage lines are brought into said cache into a least recently used (LRU) position.

20. Prefetching apparatus as defined in claim 11 wherein said deconfirmation means comprises:

means for storing an R-bit corresponding with each prefetched next sequential storage line;

means for setting said corresponding R-bit to a first state when said prefetched next sequential storage line is prefetched; and

means for setting said corresponding R-bit to a second state if said processor accesses said prefetched next sequential storage line.

21. Prefetching apparatus as defined in claim 20 wherein upon replacement of a storage line in said cache when the R-bit corresponding to said replaced storage line is in said first state, the S-bit corresponding with the storage line sequentially next preceeding said replaced storage line is set to said second state.

22. Prefetching apparatus as defined in claim 11 wherein upon a cache miss:

the S-bit corresponding with the storage line brought into said cache is set to said second state, and

if said S-bit was previously thereto in said first state, the next sequential storage line is prefetched into said cache.

23. Prefetching apparatus as defined in claim 22 wherein said S-bit corresponding with said storage line brought into said cache in response to a cache miss is reset back to said first state if said prefetched next sequential storage line is accessed by said processor before said prefetched next sequential storage line is replaced in said cache.

24. Prefetching apparatus as defined in claim 22

wherein prefetched storage lines are brought into said cache into an LRU position, and

wherein upon an access by said processor to a storage line in an LRU position in said cache,

said deconfirmation means determines whether the next preceeding sequential storage line is also stored in said cache, and

if said next preceeding sequential storage line is also stored in said cache, said changing means sets the S-bit corresponding with said next preceeding sequential storage line to said first state.