Operations controller for a fault tolerant multiple node processing system

• US 4,980,857 A
• Filed: 06/07/1989
• Issued: 12/25/1990
• Est. Priority Date: 04/15/1987
• Status: Expired due to Term

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Alliedsignal Inc.
• Inventors: Finn, Alan M., Walter, Chris J., Kieckhafer, Roger M.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US07/362,957
• Time in Patent Office: 566 Days
• Field of Search: 364/200, 364/900
• US Class Current: 714/45
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1425 by reconfiguration of node membership
• CPC Class Codes: G06F 11/1482 by means of middleware or OS functionality
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/181 Eliminating the failing redundant component
• CPC Class Codes: G06F 11/182 based on mutual exchange of the output between redundant processing components
• CPC Class Codes: G06F 11/187 Voting techniques
• CPC Class Codes: G06F 11/188 where exact match is not required
• CPC Class Codes: G06F 11/202 where processing functionality is redundant redundant communication control functionality G06F11/2005, redundant storage control functionality G06F11/2089
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A task communicator for each node in a multiple node processing system having a data memory storing data received from a voter interface which is used for the execution of tasks by an associated applications processor, a next task register storing the identification code of the next task to be executed by the applications processor received from a scheduler through a scheduler interface. An input handler passes the identification code of the next task and the data required for the execution of that task to an input FIFO register interfacing the applications processor. An output FIFO register temporarily stores the data generated by the applications processor and an output handler generates inter-node messages containing data stored in the output FIFO and passes these inter-node messages to a transmitter through a transmitter interface for transmission to all of the other nodes in the processing system.

Claims