High speed latching circuit with level shift output circuits

• US 4,982,111 A
• Filed: 01/09/1989
• Issued: 01/01/1991
• Est. Priority Date: 01/08/1988
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakaizumi, Kazuo
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/294,707
• Time in Patent Office: 722 Days
• Field of Search: 307/279, 307/291, 307/292, 307/272.1, 307/446, 307/453, 307/440, 307/443, 307/272.2, 307/475
• US Class Current: 327/208
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356026 with synchronous operation H03K3/356034, H03K3/356052 take precedence

Abstract

For prompt response to an alternation of input signal, a latching circuit comprises two NAND gates each responsive to the input signal or the inverse thereof as well as an enable signal to produce an output signal or the inverse thereof, two level shifting circuits operative to shift the output signal and the inverse thereof in voltage level, and the controller providing a voltage level to partially define the shifting range of the output signal, and each of the level shifting circuits has a capacitor and two level shifters connected to the capacitor and the controller, respectively, so that the controller has no affection of the capacitor, thereby allowing the latching operation to be improved in speed.

Claims

1. A latching circuit comprising:

a first NAND gate having a first input end receiving a first input signal, a second input end receiving an enable signal and an output end, a second NAND gate having a first input end receiving a second input signal complementary to said first input signal, a second input end receiving said enable signal and an output end, each of said first and second NAND gates including first and second transistors connected in series between the output end thereof and a first voltage terminal and having gates coupled to the first and second input ends thereof, respectively, and a load element coupled between the output end thereof and a second voltage terminal, a first level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a second level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a third level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a fourth level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a first feedback transistor having a current path connected between the output end of said first NAND gate and said first voltage terminal and a gate, a second feedback transistor having a current path connected between the output end of said second NAND gate and said first voltage terminal and a gate, means for connecting the output end of said third level shift circuit to the gate of said second feedback transistor, means for connecting the output end of said fourth level shift circuit to the gate of said first feedback transistor, a first output terminal coupled to the output end of said first level shift circuit without connection to the output end of said third level shift circuit, and a second output terminal coupled to the output end of said second level shift circuit without connection to the output end of said fourth level shift circuit.

2. A latching circuit as set forth in claim 1, in which said first level shift circuit comprises a series combination of a third depletion type field effect transistor, a first diode and a fourth depletion type field effect transistor, said first level shift circuit being coupled between said second voltage terminal and a third voltage terminal and in which said third and fourth depletion type field effect transistors have respective gate electrodes coupled to the output end of said first NAND gate and said third voltage terminal, respectively, wherein said first output terminal is coupled between said first diode and said fourth depletion type field effect transistor.

3. A latching circuit as set forth in claim 2, in which said second level shift circuit comprises a series combination of a fifth depletion type field effect transistor, a second diode and a sixth depletion type field effect transistor, said second level shift circuit being coupled between said second voltage terminal and said third voltage terminal and in which said fifth and sixth depletion type field effect transistors have respective gate electrodes coupled to the output end of said second NAND gate and said third voltage terminal, respectively, wherein said second output terminal is coupled between of said second diode and said sixth depletion type field effect transistor.

4. A latching circuit as set forth in claim 3, in which said third level shift circuit comprises a series combination of a seventh depletion type field effect transistor, a third diode and an eighth depletion type field effect transistor, said third level shift circuit being coupled between said second voltage terminal and said third voltage terminal and in which said seventh and eighth depletion type field effect transistors have respective gate electrodes coupled to the output end of said first NAND gate and said third voltage terminal, respectively, wherein the output end of said third level shift circuit is coupled between said third diode and said eighth depletion type field effect transistor.

5. A latching circuit as set forth in claim 4, in which said fourth level shift circuit comprises a series combination of a ninth depletion type field effect transistor, a fourth diode and a tenth depletion type field effect transistor, said fourth level shift circuit being coupled between said second voltage terminal and said third voltage terminal and in which said ninth and tenth depletion type field effect transistors have respective gate electrodes coupled to the output end of said second NAND gate and said third voltage terminal, respectively, wherein the output end of said fourth level shift circuit is coupled between said fourth diode and said tenth depletion type field effect transistor.

6. A latching circuit as set forth in claim 5, in which said first and second transistors are depletion type field effect transistors and in which said load element of each of said first and second NAND gates is implemented by a depletion type field effect transistor.

7. A latching circuit as set forth in claim 6, in which said first and second feedback transistors are each a depletion type field effect transistor.