Package for very large scale integrated circuit
First Claim
1. A package (10) with a semiconductor chip (12), comprising signal terminals (14) and supply terminals (15a, 15b) for outer connection of the package, a thermally conductive tagboard (20) supporting the chip, a multilayered interconnect structure (16) carried by the tagboard and at least partially surrounding the chip, said interconnect structure including:
- a decoupling device (17) comprising capacitor means (19) and superimposed conductor planes (18a, 18b) connected to said supply terminals;
outer islets (32a, 32b, 32s) disposed in proximity with the chip and comprising supply islets (32a, 32b) connected to the corresponding conductor planes (18a, 18b) and signal islets (32s) being the ends of radiating conductors of a conductive layer (34b) formed on a face of the interconnect structure and connected to the respective signal terminals (14).
0 Assignments
0 Petitions
Accused Products
Abstract
A package (10) for very large scale integrated circuit (VLSI) includes an electrically and thermally conductive tagboard (20) carrying the chip (12); supply terminals (15a) receiving a first supply potential; an interconnect structure (16) made of ceramic which surrounds the chip (12) and carries both the signal terminals (14) of the package (10) and the supply terminals (15b) receiving a second supply potential, the interconnect structure (16) incorporating the signal and supply conductors intended for the chip (12); and a decoupling device (17) including capacitors (19) and two conductor faces (18a, 18b) connected respectively to the supply terminals (15a, 15b). The decoupling by the capicitors (19) is thus done as close as possible to the conductor faces (18a and 18b) and as close as possible to the chip (12) at the level of islets (32a, 32b).
-
Citations
9 Claims
-
1. A package (10) with a semiconductor chip (12), comprising signal terminals (14) and supply terminals (15a, 15b) for outer connection of the package, a thermally conductive tagboard (20) supporting the chip, a multilayered interconnect structure (16) carried by the tagboard and at least partially surrounding the chip, said interconnect structure including:
- a decoupling device (17) comprising capacitor means (19) and superimposed conductor planes (18a, 18b) connected to said supply terminals;
outer islets (32a, 32b, 32s) disposed in proximity with the chip and comprising supply islets (32a, 32b) connected to the corresponding conductor planes (18a, 18b) and signal islets (32s) being the ends of radiating conductors of a conductive layer (34b) formed on a face of the interconnect structure and connected to the respective signal terminals (14). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- a decoupling device (17) comprising capacitor means (19) and superimposed conductor planes (18a, 18b) connected to said supply terminals;
Specification