Package for very large scale integrated circuit

• US 4,982,311 A
• Filed: 09/29/1988
• Issued: 01/01/1991
• Est. Priority Date: 09/29/1987
• Status: Expired due to Fees

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Kurzweil, Karel, Dehaine, Gerard
• Primary Examiner(s): Tolin, Gerald P.
• Application Number:
  US07/250,549
• Time in Patent Office: 824 Days
• Field of Search: 174/52.1, 174/52.4, 357/51 X, 357/74 X, 357/81, 361/380, 361/383, 361/386-388, 361/401, 361/410, 361/408, 361/414, 361/306 R, 361/308, 361/309, 361/321 R, 361/321 C, 333/33, 333/100
• US Class Current: 361/708
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10S 257/916 : Narrow band gap semiconductor material, <<1ev

Abstract

A package (10) for very large scale integrated circuit (VLSI) includes an electrically and thermally conductive tagboard (20) carrying the chip (12); supply terminals (15a) receiving a first supply potential; an interconnect structure (16) made of ceramic which surrounds the chip (12) and carries both the signal terminals (14) of the package (10) and the supply terminals (15b) receiving a second supply potential, the interconnect structure (16) incorporating the signal and supply conductors intended for the chip (12); and a decoupling device (17) including capacitors (19) and two conductor faces (18a, 18b) connected respectively to the supply terminals (15a, 15b). The decoupling by the capicitors (19) is thus done as close as possible to the conductor faces (18a and 18b) and as close as possible to the chip (12) at the level of islets (32a, 32b).

Claims

1. A package (10) with a semiconductor chip (12), comprising signal terminals (14) and supply terminals (15a, 15b) for outer connection of the package, a thermally conductive tagboard (20) supporting the chip, a multilayered interconnect structure (16) carried by the tagboard and at least partially surrounding the chip, said interconnect structure including:

a decoupling device (17) comprising capacitor means (19) and superimposed conductor planes (18a, 18b) connected to said supply terminals;

outer islets (32a, 32b, 32s) disposed in proximity with the chip and comprising supply islets (32a, 32b) connected to the corresponding conductor planes (18a, 18b) and signal islets (32s) being the ends of radiating conductors of a conductive layer (34b) formed on a face of the interconnect structure and connected to the respective signal terminals (14).

2. A package as defined by claim 1, wherein the conductive layer (34b) is a thin-film layer.

3. A package as defined by claim 1, wherein the conductive layer (34b) is connected to the signal terminals (14) of the package via at least one other conductive layer (37) of the interconnect structure.

4. A package as defined by claim 1, wherein the radiating conductors have outer peripheral ends (35) connected to the respective signal terminals of the package via at least one other conductive layer (37) of the interconnect structure.

5. A package as defined by claim 1, wherein the interconnect structure is a multilayered block of ceramic.

6. A package as defined by claim 1, wherein the interconnect structure (16) is a multilayered block of ceramic carrying said signal terminals (14) and at least one of said supply terminals (15a, 15b) of the package.

7. A package as defined by claim 1, wherein said tagboard (20) is made of an electrically conductive material and carries those of said supply terminals which are related to a first supply potential (Va) and the interconnect structure (16) carries said signal terminals (14) and the other supply terminals (15b).

8. A package as defined by claim 6, wherein the supply terminals (15a, 15b) are metal posts mounted parallel to the axis (Z'"'"'Z) of the chip.

9. A package as defined by claim 7, wherein the supply terminals (15a, 15b) are metal posts mounted parallel to the axis (Z'"'"'Z) of the chip.