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Subsampling time-domain digital filter using sparsely clocked output latch

  • US 4,982,353 A
  • Filed: 09/28/1989
  • Issued: 01/01/1991
  • Est. Priority Date: 09/28/1989
  • Status: Expired due to Fees
First Claim
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1. A clocked bit latch for latching at a submultiple of a given pulse rate, said clocked bit latch comprising:

  • means for generating a first succession of pulses at a given pulse rate;

    means for generating a second succession of pulses at a submultiple of said given pulse rate, the pulses in said second succession interleaved amongst said first succession of pulses so as not to overlap them; and

    respective initial and final clocked logic inverters, one of said respective initial and final clocked logic inverters being clocked by said first succession of pulses and the other being clocked by said second succession of pulses, said respective initial and final clocked logic inverters each having a respective input connection and having a respective output connection with associated capacitance, the input connection of said respective initial clocked logic inverter providing an input connection for said clocked bit latch, the output connection of said respective initial clocked logic inverter connecting to the input connection of said respective final clocked logic inverter, and the output connection of said respective final clocked logic inverter providing an output connection for said clocked bit latch.

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