Multiple loop parallel pipelined logic simulation system

• US 4,982,361 A
• Filed: 10/21/1985
• Issued: 01/01/1991
• Est. Priority Date: 10/26/1984
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Muramatsu, Akira, Funabashi, Motohisa, Miyaoka, Shinichiro
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US06/789,832
• Time in Patent Office: 1,898 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/578, 371/23
• US Class Current: 703/15
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The present invention is capable of registering and reading out a logical element for which the state of the output pin changes. The system includes an input side reading out circuit for reading out the kind of logical element and the states of all the input pins thereof, a decision circuit for deciding the presence of the output pin that the status change is produced on when a logical operation is carried out according to the kind of logical element, an output side reading out circuit for reading out the information related to the logical element of the output pin producing the status change, and an exchange sending circuit for sending each information read out from the output side reading out circuit to the desired registering and reading out circuit for precise high speed logic simulation of a large scale logic circuit containing MOS-type logical elements.

Claims

1. A high speed logic simulator for simulating operation of a logic circuit including a plurality of logic elements, each of the logic elements having at least one input pin and one output pin, said logic simulator comprising:

at least one registration and read out circuit means for storing a first information set corresponding to a first activated logic element, the first information set including a first logic element number for the first activated logic element, an input pin number for each input pin of said first activated logic element and a status value representing the status of each input pin of said first activated logic element, said at least one registration and read out circuit means including means for reading the first information set;

at least one first processing means for receiving the first information set read out from said at least one registration and read out means, said at least one first processing means including means for storing the first logic element number, the status value for each input pin of said first activated logic element, and a type value representing the type of said first activated logic element, and means for reading out the first logic element number, the status value of each input pin and the type value as a second information set;

at least one decision circuit means for receiving the second information set read out from said at least one first processing means, said at least one decision circuit means including means for storing output status data corresponding to said first activated logic element, means for generating an output corresponding to an output of said first activated logic element based on the received second information set, means for determining whether the generated output represents a change in the output of said first activated logic element based on the stored output status data, means for updating the stored output status data if a change in the output of said first activated logic element is detected, and means for outputting a third information set including the first activated logic element number and the output status data;

at least one second processor means for receiving the third information set output from said at least one decision circuit means and for outputting a fourth information set corresponding to a second activated logic element based on the received third information set, the fourth information set including a second activated logic element number for the second activated logic element, an input pin number for each input pin of said second activated logic element having a status change due to the output status change of said first activated logic element, and a delay time corresponding to at least the propagation delay of said second activated logic element, said at least one second processor means including means for outputting the fourth information set; and

control means for transferring the fourth information set to said at least one registration and read out means based on the second activated logic element number,

wherein said at least one registration and read out means further includes means for calculating an event time period for said second activated logic element based on a present time value and the delay time.

2. A high speed logic simulator according to claim 1, wherein the status values for at least one input pin of said first and second activated logic elements correspond to one of an undefined, driving, resistive and high impedance status.

3. A high speed logic simulator for simulating operation of a combination circuit including a plurality of logic elements each of which has at least one input pin and one output pin, said logic simulator comprising:

at least one first means including means for receiving a first number corresponding to a first logical element which has the status of one input pin thereof changed at a predetermined time, a second number corresponding to the changed input pin, the status of the changed input pin, and a delay time of said first logical element including a propagation delay time thereof, means for calculating an activated time of said first logical element, a first memory, means for storing in said first memory at a memory address corresponding to the delay time a set of values including the first number, the second number, and the status of said changed input pin, and means for reading out the first set of values from said first memory;

at least one second means including means for receiving the first set of values from said first means, a second memory, means for storing in said second memory a second set of values including the first number, the kind of logical element designated by the first number, and the status of the one input pin of said first logical element, and means for reading out the second set of values from said second memory;

at least one third means including means for receiving the second set of values from said second means, means for detecting a change in the status of an output pin of said first logical element, a third memory, means for storing in said third memory, at a memory address corresponding to the first number, a third set of values including a new status value for the output pin of said first logical element, and means for outputting a third set of values including the first number and the new status value;

at least one fourth means including means for receiving the third set of values from said third means, a fourth memory, means for reading out, from an address of said fourth memory designated by the first number, a new first number corresponding to a second logical element, a new second number for said second logical element, and a new delay time of said second logical element, and means for outputting a fourth set of values including the new first number, the new second number, the new status value and the new delay time; and

at least one fifth means for relaying the fourth set of values from said fourth means to said first means.

4. A high speed logic simulator according to claim 3, wherein at least two sets of said first, second, third and fourth means are connected in parallel with each other to said fifth means.

5. A high speed logic simulator according to claim 4, wherein said fifth means includes an exchange network for relaying the fourth set of values from one of said fourth means to a desired one of said first means.

6. A high speed logic simulator according to claim 3, wherein said at least one third means includes a buffer memory for temporarily storing the third set of values.

7. A high speed logic simulator according to claim 3, wherein the status values of each logic element include at least one of the values corresponding to a driving status, resistive status, high impedance status and indefinite status.

8. A high speed logic simulator according to claim 3, wherein the value corresponding to the status values of each logical element includes one of four values corresponding to driving status, resistive status, high impedance status and indefinite status.