Compact electronic module having a RAM device

• US 4,982,371 A
• Filed: 05/15/1989
• Issued: 01/01/1991
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lee, Robert D., Bolan, Michael L.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US07/351,759
• Time in Patent Office: 596 Days
• Field of Search: 365/229, 365/228, 365/52, 235/492, 70/278
• US Class Current: 365/228
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/047 the record carrier being shaped as a coin or a gambling token
• CPC Class Codes: G06K 19/0706 the battery being replaceable
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G06K 7/0086 the connector comprising a circuit for steering the operations of the card connector
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A very compact and economical electronic data module, which includes battery-backed memory. The module is preferably coin-shaped, and the two faces of the module are isolated from each other. The module contains logic to perform serial transfer of the whole memory content on command, using a one-wire bus.

Claims

1. A system, comprising:

a casing having exactly two mutually isolate conductive portions accessible on the exterior thereof, said casing having a sealed interior cavity;

a battery inside said casing;

volatile semiconductor memory, connected to said battery so that said battery maintains data stored in said memory;

input logic, operatively connected to first and second ones of said conductive portions of said casing, and configured to detect whether said first portion is at a first or at a second voltage, and selectably to store data in said memory accordingly;

and output logic which includes an active device connected to selectably pull said first portion of said casing toward said second voltage, but which does not include any active device connected to selectably pull said first portion of said casing toward said first voltage.

2. A system, comprising:

a casing having exactly two mutually isolated conductive portions accessibly on the exterior thereof, said casing having a sealed interior cavity;

a battery inside said cavity of casing;

volatile semiconductor memory, connected to said battery so that said battery maintains data stored in said memory;

input logic, operatively connected to first and second ones of said conductive portions of said casing, and configured to detect whether said first portion is at a first or at a second voltage, and selectably to store data in said memory accordingly;

and output logic which includes an active device connected to selectably pull said first portion of said casing toward said second voltage with low on-state impedance, but which does not include any device connected to pull said first portion of said casing toward said first voltage under any condition.

3. A system, comprising:

a casing having a ground contact, and exactly one accessible signal line;

a battery;

volatile semiconductor memory, connected to said battery so that said battery maintains data stored in said memory, said memory being configured to provide serial block access;

an N-channel field-effect transistor, connected to selectably pull said signal line toward ground potential; and

a high-impedance pull-down element, connected to pull down said signal line toward ground potential;

wherein the total impedance from said signal line to said positive terminal of said battery is always at least 10 times as much as the on-state impedance of said N-channel field-effect transistor.

4. The system of Claim 3, wherein the total impedance from said signal line to said positive terminal of said battery is at least 100 kilohms.

5. The system of Claim 3, wherein said high-impedance pull-down element consists of a very weak transistor connected to be always on.