Signal distinction circuit

• US 4,982,431 A
• Filed: 11/16/1989
• Issued: 01/01/1991
• Est. Priority Date: 11/16/1988
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanno, Masaya
• Primary Examiner(s): Isen, Forester W.
• Application Number:
  US07/438,168
• Time in Patent Office: 411 Days
• Field of Search: 381/3, 381/4, 381/7, 381/15, 381/13, 331/20, 324/78 R, 324/78 D, 324/78 F, 324/79 D, 455/67, 455/226, 84/454
• US Class Current: 381/13
• CPC Class Codes: H04B 1/1653 Detection of the presence of stereo signals and pilot signal regeneration
• CPC Class Codes: H04B 1/1692 using companding of the stereo difference signal, e.g. FMX volume compression or expansion in amplifiers H03G7/00

Abstract

A signal distinction circuit comprising a noise detector for detecting a noise included in a received signal; and a maintaining circuit for maintaining the condition of a signal outputted from a detector for detecting a discrimination signal according to a signal outputted from the noise detector so that since the noise detector and the maintaining circuit prevent the condition of a signal outputted from the distinction circuit from being changed when an inteference such as a multipath interference occuurs, an output corresponding to a received signal can be reliably obtained.

Claims

1. A signal distinction circuit having a pulse generator for generating a pulse in correspondence with the frequency of a discrimination signal;

a counter for counting the number of pulses of a clock signal according to a signal outputted from said pulse generator;

a detector for detecting said discrimination signal based on a value counted by said counter;

comprising;

a level detector for detecting the level of said discrimination signal, thus generating a reset signal for resetting said detector; and

a gate circuit for interrupting said reset signal according to the condition of a signal outputted from said detector.

2. A signal distinction circuit as claimed in claim 1, wherein said detector generates a first level output signal when a value counted by said counter reaches a predetermined value and said gate circuit interrupts a signal outputted from said level detector according to said first level signal.

3. A signal distinction circuit having a pulse generator for generating a pulse according to a discrimination signal included in a received signal;

a counter for counting the number of pulses of a clock signal according to a pulse outputted from said pulse generator;

a detector for detecting said discrimination signal according to a value counted by said counter, comprising;

a noise detector for detecting a noise included in a received signal; and

a maintaining circuit for maintaining the condition of a signal outputted from said detector according to a signal outputted from said noise detector.

4. A signal distinction circuit as claimed in claim 3, wherein said maintaining circuit includes a delayed flip flop which maintains the condition of a signal outputted from said detector;

a first signal path for passing therethrough a signal outputted from said delayed flip flop when a signal indicative of the presence of a noise is outputted from said noise detector; and

a second signal path for passing therethrough a signal outputted from said detector when a signal indicative of the presence of a noise is not generated.

5. A signal distinction circuit as claimed in claim 3, a signal outputted from said signal distinction circuit being used to selectively switch a stereophonic difference signal of a stereophonic receiver and a signal obtained by expanding a compressed stereophonic difference signal.