Method of manufacturing semiconductor devices

• US 4,983,251 A
• Filed: 06/16/1986
• Issued: 01/08/1991
• Est. Priority Date: 06/20/1985
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Pals, Jan A., Haisma, Jan, Michielsen, Theodorus M.
• Primary Examiner(s): Simmons, David
• Assistant Examiner(s): Johnson, Lori-Ann
• Application Number:
  US06/874,748
• Time in Patent Office: 1,667 Days
• Field of Search: 156/628, 156/630, 156/643, 156/662, 156/663, 156/665, 156/629, 65/17, 65/36, 65/40, 65/42, 65/43, 65/33, 65/60.5, 65/63, 65/111, 65/120, 65/155, 437/974, 437/922, 437/226, 437/62, 148/D12
• US Class Current: 438/3
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12033 : Gunn diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10S 148/012 : Bonding, e.g. electrostatic for strain gauges

Abstract

A method for manufacturing a semiconductor device comprising at least a support body and a monocrystalline semiconductor body, in which both bodies are provided with at least one flat optically smooth surface obtained by means of bulk-reducing polishing (mirror polishing), and at least the semiconductor body is then provided at the optically smooth surface with an electrically insulating layer with at least the electrically insulating layer on the semiconductor body being subjected to a bonding-activating operation, whereupon both bodies after their flat surfaces have been cleaned, are contacted with each other in a dust-free atmosphere in order to obtain a rigid mechanical connection, after which they are subjected to a heat treatment of at least 250° C., whereupon the semiconductor body is etched to a thin layer having a thickness lying between 0.05 and 100 μm.

Claims

1. A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of

(a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation,

(b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body,

(c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, wherein said bonding-activating operation is a light surface smoothing operation or a chemical etching operation,

(d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection,

(e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°

C.,

(f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and

(g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns.

2. A method according to claim 1, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.

3. A method according to claim 1, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.

4. A method according to claim 1 or claim 2 or claim 3, wherein said step of thinning by etching is carried out by an isotropic etching technique, and wherein said monocrystalline semiconductor body is intrinsic or doped.

5. A method according to claim 1 or claim 2 or claim 3 further comprising:

etching said thinned monocrystalline semiconductor body to form a plurality of separate regions,

closing, by thermal oxidation or by deposition, spaces between said separate regions wherein deposition comprises depositing an insulating groove filling in said spaces between said separate regions,

depositing insulating filling on said separate regions to a thickness exceeding the thickness of said thinned monocrystalline semiconductor body,

planarizing the monocrystalline semiconductor body with the insulating filling thereon to thereby form a support of insulated semiconductor regions the surface of which is entirely flat.

6. A method according to claim 1 or claim 2 or claim 3 wherein a portion of said support body is formed with semiconductor material of AIII-BV type, said portion being contiguous with said optically smooth surface, wherein said monocrystalline semiconductor body is formed of silicon and said electrically insulating layer is formed of thermally grown silicon oxide, and further comprising:

removing portions of said monocrystalline semiconductor body to said silicon oxide,

forming doped regions constituting source and drain regions in said AIII-BV semiconductor material, and

forming gate regions from said electrically insulating layer of silicon oxide between said doped regions for a MOS FET of said AIII-BV semiconductor material.

7. A method according to claim 6, wherein said AIII-BV semiconductor material is gallium arsenide.

8. A method according to claim 1 or claim 2 or claim 3, wherein said support body is formed with both electrical insulating properties and active bulk properties.

9. A method according to claim 8, wherein said active bulk properties include at least one of magnetic properties, piezoelectrical properties, photoreactive properties, and electrooptical properties.

10. A method according to claim 1 or claim 2 or claim 3, wherein said support body is formed with electrically insulating properties, layerwise active properties, and properties for producing static-magnetic surface waves.

11. A method according to claim 10, wherein said layerwise active properties include generating acoustic surface waves.

12. A method according to claim 1 or 2 or 3 further comprising:

forming IC structures in the thinned monocrystalline semiconductor body to thereby form a first embossed outer surface, said IC structures forming a first register,

depositing a silicon oxide layer on said first embossed outer surface,

planarizing said silicon oxide layer to form an insulating layer of small thickness,

forming a second thinned monocrystalline semiconductor body having an electrically insulating layer on said planarized silicon oxide layer,

forming IC structures in said second thinned monocrystalline semiconductor body to thereby form a second embossed outer surface, said IC structures forming a second register,

carrying out a repetition of analogous steps to form additional ICs thereby forming a three-dimensional stack IC.

13. A method according to claim 12, wherein at least one Peltier element is formed in at least one of said registers for cooling said three-dimensional stack IC.

14. A method according to claim 12, wherein at least one of said registers is used to accommodate components occupying a large surface area.

15. A method according to claim 14, wherein said components are capacitors.

16. A method according to claim 12 further comprising:

etching holes into said registers at location accommodating electrical connections, and

filling said holes with an electrically conducting material.

17. A method according to claim 12, further comprising providing electrical conductors at the outer circumference of said three-dimensional stack IC to establish connections between different registers.

18. A method according to claim 12 further comprising:

providing an optical fiber arrangement to feed light energy to at least one of said registers, and

providing transparent channels in said three dimensional stack IC to transport said light energy to said registers.

19. A method according to claim 18, wherein said transparent channels are formed in the plane of circuits to be energized in said registers.

20. A method according to claim 18, wherein said transparent channels are formed to transmit light energy at right angles to planes of circuits to be energized in said registers.

21. A method according to claim 12, wherein said monocrystalline semiconductor bodies to be connected are formed (1) of semiconductor material for fulfilling mainly electrical functions, and (2) of semiconductor material for fulfilling mainly optical functions.

22. A method according to claim 21, wherein said semiconductor material for fulfilling mainly optical functions is configured with light-dissipating leads for dissipating light energy to the outside of said semiconductor structure or for internally converting light energy into an electrical signal.

23. A method according to claim 21, further comprising forming insulating channels in said registers to have a dual function of electrical insulation and light conduction.

24. A method according to claim 1, wherein said light surface smoothing operation includes smoothing a surface of said electrically insulating layer by removing microscopic unevenness.

25. A method according to claim 1, wherein said chemical etching operation includes lightly etching a surface of said electrically insulating layer.

26. A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of

(a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation,

(b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body,

(c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation,

(d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection,

(e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°

C.,

(f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and

(g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns,

wherein said monocrystalline semiconductor body includes a highly doped first layer and a weakly doped second layer epitaxially grown on said first layer, and wherein said step of thinning by etching is carried out by an electrochemical etch treatment to etch away completely said first layer, said electrochemical etch treatment being stopped at said second layer.

27. A method according to claim 26, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.

28. A method according to claim 26, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.

29. A method according to claim 26, wherein said bonding-activating operation is a light surface smoothing operation.

30. A method according to claim 26, wherein said bonding-activating operation is a chemical etching operation.

31. A method according to claim 26, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200°

C., and densifying said layer to glass at a temperature of at least 800°

C.

32. A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of

(a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer,

(b) forming a magnetic domain memory or Bloch line memory,

(c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation,

(d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body,

(e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation,

(f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection,

(g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°

C.,

(h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and

(i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns,

(j) forming semiconductor elements in said monocrystalline semiconductor body to obtain an electrical circuit for controlling said magnetic domain memory or saiud bloch line memory.

33. A method according to claim 32, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.

34. A method according to claim 32, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.

35. A method according to claim 32, wherein said bonding-activating operation is a light surface smoothing operation.

36. A method according to claim 32, wherein said bonding-activating operation is a chemical etching operation.

37. A method according to claim 32, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200°

C., and densifying said layer to glass at a temperature of at least 800°

C.

38. A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of

(a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer,

(b) forming a magnetic domain memory or Bloch line memory,

(c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation,

(d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body,

(e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation,

(f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection,

(g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°

C.,

(h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and

(i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns,

(j) forming semiconductor elements as an electrical memory to provide an interaction between said magnetic memory and said electric memory.

39. A method according to claim 38, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.

40. A method according to claim 38, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.

41. A method according to claim 38, wherein said bonding-activating operation is a light surface smoothing operation.

42. A method according to claim 38, wherein said bonding-activating operation is a chemical etching operation.

43. A method according to claim 38, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200°

C., and densifying said layer to glass at a temperature of at least 800°

C.