High-density electronic modules - process and product

• US 4,983,533 A
• Filed: 10/28/1987
• Issued: 01/08/1991
• Est. Priority Date: 10/28/1987
• Status: Expired due to Term

• Current Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Go, Tiong C.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Griffis, Andrew
• Application Number:
  US07/114,415
• Time in Patent Office: 1,168 Days
• Field of Search: 437/208, 437/915, 437/51.8, 437/7, 357/74, 357/75, 361/388, 361/389
• US Class Current: 438/12
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 7/023 Stackable modules
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A high-density electronic module is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips, each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane. Where heat extraction augmentation is needed, additional interleaved layers are included in the stacks which have high thermal conductivity, and are electrical insulators. These interleaved layers may carry rerouting electrical conductors. Bonding bumps are formed at appropriate points on the access plane. A stack-supporting substrate is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or stack-supporting substrate, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrate face is placed on the access plane of the stack, their bonding bumps are microscopically aligned, and then bonded together under heat and/or pressure.

Claims

1. A method for fabricating a package containing high density electronic circuitry, comprising:

providing a plurality of integrated circuit chips, each having a multiplicity of closely-spaced electrical leads at one or more edges thereof;

interspersing in the stack of integrated circuit chips a plurality of interleaved layers formed of material having high thermal conductivity to extract heat from the stack.

stacking and bonding the integrated circuit chips and the interleaved layers in a structure having an access plane, on which plane there is a two-dimensional array of closely-spaced electrical leads;

forming on the access plane, in direct or indirect electrical contact with the chip leads, a plurality of conductive lines and a plurality of conductive terminals;

providing a stack-carrying substrate adapted to support the stacked chips and having formed thereon a plurality of conductive lines and a plurality of conductive terminals;

the conductive terminals on the access plane being located in precise matched relationship with the conductive terminals on the stack-carrying substrate; and

securing the stacked structure to the stack-carrying substrate, with the conductive terminals on the access plane separately contacting the conductive terminals on the substrate.

2. The method of claim 1 in which the integrated circuit chips are gallium arsenide chips.

3. The method of claim 1 in which the material of the interleaved layers is beryllium oxide.

4. The method of claim 1 which also comprises:

forming on at least some of the interleaved layers electrical conductors which interconnect the leads on the integrated circuit chips with the conductive lines on the access plane.

5. The method of claim 1 in which the leads on the integrated circuit chips connect directly to the conductive lines on the access plane.

6. A method for fabricating a package containing high-density electronic circuitry, comprising:

providing a plurality of separate layers, at least some of which are IC chips, and at least some of which have electrical conductors terminating at a common interconnect plane;

stacking and bonding the layers to form an integrated stack having electrical terminals on its interconnect plane

providing a stack-carrying substrate having printed circuitry thereon including a separate IC chip conductor available for connection to each IC chip, an interlinking conductor interconnecting the IC chip conductors, and a reduced number of conductors leading from the interlinking conductor toward external circuitry;

securing the integrated stack to the stack-carrying substrate with each IC chip in the stack electrically connected to a separate conductor on the substrate;

determining whether any stacked IC chip is defective; and

removing portions of the interlinking conductor on the substrate to isolate the defective IC chip from the external circuitry.

7. A method for fabricating a package containing high density electronic circuitry, comprising:

providing a plurality of integrated circuit chips, each having a multiplicity of closely-spaced electrical leads at one or more edges thereof;

interspersing in the stack of integrated circuit chips a plurality of interleaved layers formed of material having high thermal conductivity to extract heat from the stack;

stacking and bonding the integrated circuit chips and the interleaved layers in a structure having an access plane, on which plane there is a two-dimensional array of closely-spaced electrical leads;

forming on the access plane, in direct or indirect electrical contact with the chip leads, a plurality of conductive lines;

providing a stack-carrying substrate adapted to support the stacked chips and having formed thereon a plurality of conductive lines;

securing the stacked structure to the stack-carrying substrate; and

providing electrical connections between the conductive lines on the access plane and the conductive lines on the stack-carrying substrate.

8. The method of claim 7 in which the integrated circuit chips are gallium arsenide chips.

9. The method of claim 7 in which the material of the interleaved layers is beryllium oxide.

10. The method of claim 7 which also comprises:

forming on at least some of the interleaved layers electrical conductors which interconnect the leads on the integrated circuit chips with the conductive lines on the access plane.

11. The method of claim 7 in which the leads on the integrated circuit chips connect directly to the conductive lines on the access plane.