Vertical DMOS transistor fabrication process

• US 4,983,535 A
• Filed: 12/28/1988
• Issued: 01/08/1991
• Est. Priority Date: 10/15/1981
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Quach, T. N.
• Application Number:
  US07/292,668
• Time in Patent Office: 741 Days
• Field of Search: 357/23.4, 357/23.1, 357/15, 437/178, 437/179, 437/38, 437/41, 437/52, 437/203, 437/29, 437/40, 437/44, 437/192, 437/201, 148/DIG. 105, 148/DIG. 126
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: Y10S 148/105 Masks, metal
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A process for fabricating a vertical DMOS transistor is set forth. The starting material is a heavily doped silicon wafer which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on.

Claims

1. A process for fabricating a vertical DMOS transistor, having source, drain, gate and body regions, comprising the steps:

providing a high conductivity semiconductor substrate wafer having a first conductivity type and a similar conductivity type epitaxial layer thereon;

forming an opposite conductivity type body region extending part way through said epitaxial layer;

forming a heavily doped opposite conductivity type region surrounding said body region to define said DMOS transistor and to provide a deep body contact;

forming a refractory metal layer over said body region to provide a contact thereto;

forming a gate region within said body region by etching a trench in said epitaxial layer to completely penetrate said body region, forming a gate oxide on the walls of said trench, filling said trench with doped polysilicon and removing the excess polysilicon to leave said trench filled with conductive polysilicon to provide said gate electrode of said DMOS transistor; and

forming contacts to said refractory metal, said conductive polysilicon, said deep body contact region and said substrate wafer,

wherein said refractory metal acts as said source of said DMOS transistor, and

wherein said refractory metal also forms an ohmic connection to said deep body contact region.

2. The process of claim 1 wherein said substrate wafer is composed of N+ silicon, said epitaxial layer is composed of N type silicon, said body region is composed of P type silicon and said deep body contact region is composed of P+ silicon.

3. The process of claim 1 wherein said substrate wafer is composed of P+ silicon, said epitaxial layer is composed of P type silicon, said body region is composed of N type silicon and said deep body contact region is composed of N+ silicon.

4. The process of claim 1 wherein said trench is formed by means of an anisotropic reactive ion etching step.

5. The process of claim 4 wherein said refractory metal is formed using a catalyzed metal deposition step in which the metal is deposited only upon an exposed silicon surface and wherein said refractory metal is employed as a mask for said anisotropic reactive ion etch.