High speed switch matrix

• US 4,983,865 A
• Filed: 01/25/1989
• Issued: 01/08/1991
• Est. Priority Date: 01/25/1989
• Status: Expired due to Fees

• Current Assignee: Pacific Monolithics Incorporated (Iowave, Inc.)
• Original Assignee: Pacific Monolithics Incorporated (Iowave, Inc.)
• Inventors: Moghe, Sanjay B., Ho, Pang-Ting
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/301,491
• Time in Patent Office: 713 Days
• Field of Search: 333/103, 333/100, 333/124, 328/156, 328/104, 328/105, 328/137, 328/152, 328/153, 307/271, 307/242, 307/241, 307/571
• US Class Current: 327/404
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A switch matrix for particular use in microwave monolithic integrated circuits has FET-based switch elements with at least a combined total of two gates. Embodiments include the use of single and dual gate FETs. A preferred embodiment includes cascode-coupled FETs in series with inductances between input and output terminals. The input is taken from an artificial transmission line formed of a plurality of series-coupled inductors or from the junctions of series-coupled pairs of mutually coupled inductors.

Claims

1. A switch matrix, usable with control means generating switch control signals, comprising:

an input terminal and first and second output terminals;

first field-effect transistor (FET) switch means controllable for coupling selectively said input terminal to said first output terminal, and having two gates and a drain, a first of said gates of said first FET switch means being coupled to said input terminal, the second of said gates of said first FET switch means being connectable to the control means for receiving a control signal, and said drain of said first FET switch means being coupled to said first output terminal; and

second field-effect transistor (FET) switch means also having two gates and a drain, a first of said gates of said second FET switch means being coupled to said input terminal, the second of said gates of said second FET switch means being connectable to the control means for receiving a control signal, and said drain of said second FET switch means being coupled to said second output terminal.

2. A matrix according to claim 1 wherein each of said first and second FET switch means comprises a first dual-gate FET means.

3. A matrix according to claim 2 wherein each of said first and second FET switch means further comprise a second dual-gate FET means coupled in series with said first FET means, and having a first gate coupled to the drain of said first dual-gate FET means, a second gate connectable to the control means for receiving a control signal, and a drain coupled to said respective output terminal.

4. A matrix according to claim 1 wherein said first and second FET switch means each further comprises a pair of series-connected single-gate FET means, each having a gate, source and drain, with said gate of a first of said single-gate FET means being coupled to said input terminal, said source of said first single-gate FET means coupled to ground, said drain of said first single-gate FET means coupled to said source of the second of said single-gate FET means, said gate of said second single-gate FET means connectable to the control means for receiving a control signal, and said drain of said second single-gate FET means coupled to the respective one of said first and second output terminals.

5. A matrix according to claim 4 wherein each of said FET switch means further comprises inductor means coupled in series between said drain of said first FET means and said source of said second FET means.

6. A matrix according to claim 1 further comprising a first inductor means coupling said input terminal to said first gate of said first FET switch means, and a second inductor means coupled said input terminal, through said first inductor means, to said first gate of said second FET switch means.

7. A matrix according to claim 6 further comprising third inductor means connected in series with said first and second inductor means for coupling said input terminal to ground, with said third inductor means being coupled to said input terminal through said first and second inductor means.

8. A matrix according to claim 6 further comprising third and fourth inductor means connected in series with said first and second inductor means for coupling said input terminal to ground, with said first and second inductor means being mutually coupled and said third and fourth inductor means being mutually coupled.

9. A switch matrix, usable with a control means generating switch control signals, comprising:

an input terminal and first and second output terminals;

a first pair of mutually coupled inductor means, a second pair of mutually coupled inductor means, and impedance means serially connected for coupling said input terminal to ground, with each pair of inductor means joining at a node;

first switch means controllable for coupling selectively said input terminal to said first output terminal, said first switch means comprising first and second field effect transistor (FET) means coupled in series between said input terminal and said first output terminal, said first FET means having a common source, a gate coupled to said input terminal, and a drain, and said second FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said first FET means, and a drain coupled to said first output terminal, and fifth inductor means coupled between said node between said first pair of inductor means and said gate of said first FET means, sixth inductor means coupled between said first and second FET means, and seventh inductor means coupled between said second FET means and said first output terminal; and

second switch means controllable for coupling selectively said input terminal to said second output terminal through said first pair of mutually coupled inductor means, said second switch means comprising third and fourth field effect transistor (FET) means coupled in series between said input terminal and said second output terminal, said third FET input terminal, and a drain, and said fourth FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said third FET means, and a drain coupled to said second output terminal, and eighth inductor means coupled between said node between said second pair of inductor means and said gate of said third FET means, ninth inductor means coupled between said third and fourth FET means, and tenth inductor means coupled between said fourth FET means and said second output terminal.

10. A matrix according to claim 9 wherein said FET means are all single-gate FETs.

11. A switch matrix, usable with control means generating switch control signals, comprising:

first and second input terminals and an output terminal;

first field-effect transistor (FET) switch means controllable for coupling selectively said first input terminal to said output terminal, and having two gates and a drain, a first of said gates of said first FET switch means being coupled to said first input terminal, the second of said gates of said first FET switch means being connectable to the control means for receiving a control signal, and said drain of said first FET switch means being coupled to said output terminal; and

second field-effect transistor (FET) switch means also having two gates and a drain, a first of said gates of said second FET switch means being coupled to said second input terminal, the second of said gates of said second FET means being connectable to the control means for receiving a control signal, and said drain of said second FET switch means being coupled to said output terminal.

14. A matrix according to claim 11 wherein said first and second FET switch means each further comprises a pair of series-connected single-gate FET means, each having a gate, source and drain, with said gate of a first of said single-gate FET means being coupled to the respective one of said input terminals, said source of said first single-gate FET means being coupled to ground, said drain of said first single-gate FET means being coupled to said source of the second of said single-gate FET means, said gate of said second single-gate FET means being connectable to the control means for receiving a control signal, and said drain of said second single-gate FET means being coupled to said output terminal.

15. A matrix according to claim 14 wherein each of said FET switch means further comprises inductor means coupled in series between said drain of said first FET means and said source of said second FET means.

16. A matrix according to claim 11 further comprising a first inductor means coupling said drain of said first FET switch means to said output terminal, and a second inductor means coupling said drain of said second FET switch means through said first inductor means to said output terminal.

17. A matrix according to claim 16 further comprising third inductor means connected in series with said first and second inductor means for coupling said output terminal to ground, with said third inductor means being coupled to said output terminal through said first and second inductor means.

18. A matrix according to claim 16 further comprising third and fourth inductor means connected in series with said first and second inductor means for coupling said output terminal to ground, with said first and second inductor means being mutually coupled and said third and fourth inductor means being mutually coupled.

12. A matrix according to claim 27 wherein each of said first and second FET switch means comprises a first dual-gate FET means.

13. A matrix according to claim 12 wherein each of said first and second FET switch means further comprise a second dual-gate FET means coupled in series with said first FET means, and having a first gate coupled to the drain of said first dual-gate FET means, a second gate connectable to the control means for receiving a control signal, and a drain coupled to said output terminal.

19. A switch matrix, usable with a control means generating switch control signals, comprising:

first and second input terminals and an output terminal;

first, second and third inductor means, and impedance means serially connected for coupling said output terminal to ground, with each pair of inductor means joining at a node;

first switch means controllable for coupling selectively said first input terminal to said output terminal, said first switch means comprising first and second field effect transistor (FET) means coupled in series between said first input terminal and said output terminal, said first FET means having a common source, a gate coupled to said first input terminal, and a drain, and said second FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said first FET means, and a drain coupled to said output terminal, and fourth inductor means coupled between said first input terminal and said gate of said first FET means, fifth inductor means coupled between said first and second FET means, and sixth inductor means coupled between said drain of said second FET means and said node between said first and second inductor means; and

second switch means controllable for coupling selectively said second input terminal to said output terminal through said first and second inductor means, said second switch means comprising third and fourth field effect transistor (FET) means coupled in series between said second input terminal and said output terminal, said third FET means having a common source, a gate coupled to said second input terminal, and a drain, and said fourth FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said rain of said third FET means, and a drain coupled to said output terminal, and eighth inductor means coupled between said second input terminal and said gate of said third FET means, ninth inductor means coupled between said third and fourth FET means, and tenth inductor means coupled between said fourth FET means and said node between said second and third inductor means.

20. A matrix according to claim 19 wherein said FET means are all single-gate FETS.