High speed switch matrix
First Claim
Patent Images
1. A switch matrix, usable with control means generating switch control signals, comprising:
- an input terminal and first and second output terminals;
first field-effect transistor (FET) switch means controllable for coupling selectively said input terminal to said first output terminal, and having two gates and a drain, a first of said gates of said first FET switch means being coupled to said input terminal, the second of said gates of said first FET switch means being connectable to the control means for receiving a control signal, and said drain of said first FET switch means being coupled to said first output terminal; and
second field-effect transistor (FET) switch means also having two gates and a drain, a first of said gates of said second FET switch means being coupled to said input terminal, the second of said gates of said second FET switch means being connectable to the control means for receiving a control signal, and said drain of said second FET switch means being coupled to said second output terminal.
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Abstract
A switch matrix for particular use in microwave monolithic integrated circuits has FET-based switch elements with at least a combined total of two gates. Embodiments include the use of single and dual gate FETs. A preferred embodiment includes cascode-coupled FETs in series with inductances between input and output terminals. The input is taken from an artificial transmission line formed of a plurality of series-coupled inductors or from the junctions of series-coupled pairs of mutually coupled inductors.
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Citations
20 Claims
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1. A switch matrix, usable with control means generating switch control signals, comprising:
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an input terminal and first and second output terminals; first field-effect transistor (FET) switch means controllable for coupling selectively said input terminal to said first output terminal, and having two gates and a drain, a first of said gates of said first FET switch means being coupled to said input terminal, the second of said gates of said first FET switch means being connectable to the control means for receiving a control signal, and said drain of said first FET switch means being coupled to said first output terminal; and second field-effect transistor (FET) switch means also having two gates and a drain, a first of said gates of said second FET switch means being coupled to said input terminal, the second of said gates of said second FET switch means being connectable to the control means for receiving a control signal, and said drain of said second FET switch means being coupled to said second output terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A switch matrix, usable with a control means generating switch control signals, comprising:
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an input terminal and first and second output terminals; a first pair of mutually coupled inductor means, a second pair of mutually coupled inductor means, and impedance means serially connected for coupling said input terminal to ground, with each pair of inductor means joining at a node; first switch means controllable for coupling selectively said input terminal to said first output terminal, said first switch means comprising first and second field effect transistor (FET) means coupled in series between said input terminal and said first output terminal, said first FET means having a common source, a gate coupled to said input terminal, and a drain, and said second FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said first FET means, and a drain coupled to said first output terminal, and fifth inductor means coupled between said node between said first pair of inductor means and said gate of said first FET means, sixth inductor means coupled between said first and second FET means, and seventh inductor means coupled between said second FET means and said first output terminal; and second switch means controllable for coupling selectively said input terminal to said second output terminal through said first pair of mutually coupled inductor means, said second switch means comprising third and fourth field effect transistor (FET) means coupled in series between said input terminal and said second output terminal, said third FET input terminal, and a drain, and said fourth FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said third FET means, and a drain coupled to said second output terminal, and eighth inductor means coupled between said node between said second pair of inductor means and said gate of said third FET means, ninth inductor means coupled between said third and fourth FET means, and tenth inductor means coupled between said fourth FET means and said second output terminal. - View Dependent Claims (10)
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11. A switch matrix, usable with control means generating switch control signals, comprising:
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first and second input terminals and an output terminal; first field-effect transistor (FET) switch means controllable for coupling selectively said first input terminal to said output terminal, and having two gates and a drain, a first of said gates of said first FET switch means being coupled to said first input terminal, the second of said gates of said first FET switch means being connectable to the control means for receiving a control signal, and said drain of said first FET switch means being coupled to said output terminal; and second field-effect transistor (FET) switch means also having two gates and a drain, a first of said gates of said second FET switch means being coupled to said second input terminal, the second of said gates of said second FET means being connectable to the control means for receiving a control signal, and said drain of said second FET switch means being coupled to said output terminal. - View Dependent Claims (14, 15, 16, 17, 18)
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- 12. A matrix according to claim 27 wherein each of said first and second FET switch means comprises a first dual-gate FET means.
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19. A switch matrix, usable with a control means generating switch control signals, comprising:
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first and second input terminals and an output terminal; first, second and third inductor means, and impedance means serially connected for coupling said output terminal to ground, with each pair of inductor means joining at a node; first switch means controllable for coupling selectively said first input terminal to said output terminal, said first switch means comprising first and second field effect transistor (FET) means coupled in series between said first input terminal and said output terminal, said first FET means having a common source, a gate coupled to said first input terminal, and a drain, and said second FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said drain of said first FET means, and a drain coupled to said output terminal, and fourth inductor means coupled between said first input terminal and said gate of said first FET means, fifth inductor means coupled between said first and second FET means, and sixth inductor means coupled between said drain of said second FET means and said node between said first and second inductor means; and second switch means controllable for coupling selectively said second input terminal to said output terminal through said first and second inductor means, said second switch means comprising third and fourth field effect transistor (FET) means coupled in series between said second input terminal and said output terminal, said third FET means having a common source, a gate coupled to said second input terminal, and a drain, and said fourth FET means having a common gate connectable to the control means for receiving a control signal, a source coupled to said rain of said third FET means, and a drain coupled to said output terminal, and eighth inductor means coupled between said second input terminal and said gate of said third FET means, ninth inductor means coupled between said third and fourth FET means, and tenth inductor means coupled between said fourth FET means and said node between said second and third inductor means. - View Dependent Claims (20)
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Specification