Edge transition insensitive delay line system and method

• US 4,984,255 A
• Filed: 11/15/1989
• Issued: 01/08/1991
• Est. Priority Date: 11/15/1989
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Davis, Craig M., Tietz, Gary W.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/436,897
• Time in Patent Office: 419 Days
• Field of Search: 375/106, 375/113, 375/110, 375/118, 375/119, 375/120, 328/63, 328/155, 207/262, 331/47, 331/57, 331/25
• US Class Current: 375/354
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system (100, 50, 300) for recovering a clock signal from a serial data signal (102) having rising (204) and falling (206) transitions. The transistions (204, 206) are detected by a transition detector (11, 12, 108, 110) which generates a transition signal (13a, 13b, 109, 111) having a first logic state when a rising (204) or falling (206) transition is detected. The system (100, 50, 300) includes a delay device (22, 120, 122) which delays the transition signal (13a, 13b, 109, 111) by a preselected time period and a gating device (24, 124, 126) responsive to the transition signal (13a, 13b, 109, 111). The gating device (24, 124, 126) is enabled by the transition signal (13a, 13b, 109, 111) when the signal is the first logic state, thereby permitting a system generated clock signal (148) to propagate to a phase comparison system (132, 134, 176, 178, G 1, G4) for comparison with the delayed transition signal (23, 128, 130). The phase comparison system (132, 134, 178, G1, G4) generate a correction signal (30) indicative of the phase difference between the compared signals (23, 25, 144, 152, 130, 154) such that the transitions in clock signal (148) generated are in synchronization with the data transitions (204, 206).

Claims

1. A system for recovering a clock signal from a data signal having rising and falling data transitions, comprising:

detection means for detecting data transitions in the data signal;

transition means for generating a transition signal indicative of a detected data transition, wherein the transition signal has a logic level associated therewith and wherein the logic level is a first level when a transition is detected;

delay means for delaying the transition signal by a preselected time period;

means responsive to a correction signal for generating a clock signal having clock transitions which occur in synchronization with the data transitions;

comparison means for comparing the delayed transition signal to a reference signal and for generating the correction signal indicative of a phase difference therebetween; and

gating means responsive to the first logic level of the transition signal for supplying the clock signal to the comparison means such that the clock signal is the reference signal.

2. The system of claim 1, wherein the detecting means, comprises:

means responsive to a rising data transition in the data signal; and

means responsive to a falling data transition in the data signal.

3. The system of claim 1, wherein the transition means generates a rising transition signal having the first logic level when a rising data transition is detected and generates a falling transition signal having the first logic level when a falling data transition is detected.

4. The system of claim 1, where the first logic level is a logic high.

5. The system of claim 3, wherein the transition signal comprises the rising transition signal and the falling transition signal.

6. The system of claim 3, wherein the gating means includes:

rising gating means responsive to the rising transition signal for supplying the clock signal; and

falling gating means responsive to the falling transition signal for supplying the clock signal, wherein the rising gating means supplies the clock signal as the reference signal and the falling gating means supplies the clock signal as the reference signal.

7. The system of claim 6, wherein the rising gating means includes a pulse gate and the falling gating means includes a pulse gate.

8. The system of claim 7, wherein the pulse gate is a D-type flip flop.

9. The system of claim 3, wherein the delay means further comprises:

rising delay means for delaying the rising transition signal by the preselected time period; and

falling delay means for delaying the falling transition signal by the preselected time period.

10. The system of claim 1, wherein the clock transitions occur in synchronization with the transitions in the data signal when the correction signal is about zero.

11. The system of claim 1, wherein the preselected time period is about equal to one half a data cell window, where the data cell window is the time interval during which the transition occurs in the data signal.

12. The system of claim 1, wherein the means for generating the clock signal has a clock cycle associated therewith and wherein the preselected time period is proportional to the clock cycle.

13. The system of claim 1, wherein the means for generating the clock signal, comprises:

a phase comparator which compares the delayed transition signal and the reference signal and generates the correction signal; and

a voltage controlled oscillator responsive to the correction signal to generate the clock signal wherein the clock transitions and the data transitions occur in synchronization when the correction signal is about zero.

14. The system of claim 3, wherein the comparison means includes:

rising comparison means for comparing the rising transition signal with the clock signal and for generating a rising comparison signal; and

falling comparison means for comparing the falling transition signal with the clock signal and for generating a falling comparison signal, wherein the comparison signal includes the rising and the falling comparison signals.

15. A system for regenerating a clock signal from a data signal having rising and falling data transitions, comprising:

rising detecting means for detecting a rising data transition in the data signal;

negative detecting means for detecting a falling data transition in the data signal;

rising transition means for generating a rising transition signal indicative of the detected rising transition, wherein the rising transition signal has a logic level associated therewith wherein the logic level is a preselected level when a rising transition is detected;

falling transition means for generating a falling transition signal indicative of the detected falling data transition in the data signal, wherein the falling transition signal has a logic level associated therewith wherein the logic level is the preselected level when a falling transition is detected;

delay means for delaying the data signal by a preselected time period;

means responsive to a correction signal for generating a clock signal having clock transitions which occur in synchronization with the data transitions;

comparison means for comparing the delayed data signal to a reference signal and for generating the correction signal indicative of a phase difference therebetween; and

gating means responsive to the rising transition signal and the falling transition signal for supplying the clock signal to the comparison means when a transition is detected such that the clock signal is the reference signal.

16. The system of claim 15, wherein the delay means includes:

first delay means for delaying the rising transition signal; and

second delay means for delaying the falling transition signal.

17. A method for recovering a clock signal from a data signal having rising and falling data transitions, comprising:

detecting a data transitions in the data signal;

generating a transition signal indicative of a detected transition, wherein the transition signal has a logic level associated therewith and wherein the logic level is a first preselected level when a transition is detected;

delaying the transition signal by a preselected time period;

generating a clock signal having clock transitions which occur in synchronization with the data transitions in response to a correction signal;

comparing in a means for comparing the delayed transition signal to a reference signal and generating the correction signal indicative of a phase difference therebetween; and

supplying the clock signal to the means for comparing in response to the first logic level of the transition signal such that the clock signal is the reference signal.

18. The method of claim 17, wherein the step of generating the transition signal further includes the steps of:

generating a rising transition signal when a rising data transition is detected in the data signal;

generating a falling transition signal when a falling data transition is detected in the data signal, wherein the transition signal includes the rising transition signal and the falling transition signal.

19. The method claim 18, wherein the step of supplying further includes the steps of:

supplying the clock signal as the reference signal in response to the rising transition signal; and

supplying the clock signal as the reference signal in response to the falling transition signal.

20. The method of claim 18, wherein the step of delaying further comprises the steps of:

delaying the rising transition signal by the preselected time period and delaying the falling transition signal by the preselected time period.

21. The method of claim 18, wherein the step of comparing, further includes the steps of:

comparing the rising transition signal with the clock signal and generating a rising comparison signal; and

comparing the falling transition signal with the clock signal and generating a falling comparison signal wherein the comparison signal includes the rising and the falling comparison signals.

22. A system for recovering a clock signal from a data signal having logic state transitions, the system comprising:

detection means for detecting logic state transitions in the data signal;

transition means for generating a transition signal indicative of a detected logic state transition;

delay means for delaying the transition signal by a preselected time period;

means responsive to a correction signal for generating a clock signal having clock transitions which occur in synchronization with the logic state transitions;

comparison means for comparing the delayed transition signal to a reference signal and for generating the correction signal indicative of a phase difference between the reference signal and the delayed transition signal; and

gating means responsive to the transition signal for supplying the clock signal to the comparison means such that the clock signal is the reference signal.

23. The system of claim 22, wherein the logic state transitions include first logic state transitions from a high logic state to a low logic state and second logic state transitions from a low logic state to a high logic state and wherein:

the transition means comprises means for detecting first logic state transitions and means for detecting second logic state transitions; and

the delay means includes

first delay means for delaying the data signal when a first logic state transition is detected; and

second delay means for delaying the data signal when a second logic state transition is detected.

24. A system for regenerating a clock signal from a data signal having logic state transitions, the system comprising:

first detection means for detecting a first logic state transition in the data signal;

second detection means for detecting a second logic state transition in the data signal;

first transition means for generating a first transition signal when a first logic state transition is detected;

second transition means for generating a second logic state transition signal when a second logic state transition is detected;

first delay means for delaying the first transition signal by a preselected time period;

second delay means for delaying the second transition signal by the preselected time period;

first comparison means for comparing the delayed first transition signal to a reference signal and for generating a first correction signal indicative of a phase difference between the delayed first transition signal and the reference signal;

second comparison means for comparing the delayed second transition signal to the reference signal and for generating a second correction signal indicative of a phase difference between the delayed second transition signal and the reference signal;

means responsive to the first correction signal and the second correction signal for generating a clock signal having clock transitions which occur in synchronization with the detected first and second logic state transition;

first gating means for supplying the clock signal to the first comparison means when a first logic transition is detected; and

second gating means for supplying the clock signal to the second comparison means when a second logic transition is detected.