Method of assembling stacks of integrated circuit dies

• US 4,984,358 A
• Filed: 06/18/1990
• Issued: 01/15/1991
• Est. Priority Date: 03/10/1989
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Nelson, Bradley H.
• Primary Examiner(s): ECHOLS, PERCY W
• Application Number:
  US07/539,769
• Time in Patent Office: 211 Days
• Field of Search: 29/830, 29/854, 29/855, 29/885, 29/412-415, 437/226, 437/227
• US Class Current: 438/109
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06182 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/06187 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32105 the layer connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/32238 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49224 : with coating
• CPC Class Codes: Y10T 29/49789 : Obtaining plural product pieces from unitary workpiece
• CPC Class Codes: Y10T 29/4979 : Breaking through weakened portion
• CPC Class Codes: Y10T 29/49792 : Dividing through modified portion

Abstract

Integrated circuit dies, while still in wafer form, are prepared for stacking without requiring packaging. Holes are made through a wafer having a plurality of integrated circuit dies and are placed between the dies and adjacent the die pads. A layer of insulating material is placed on the wafer and in the outer periphery of the holes. An electrically conductive connection is made between the top of each pad and the inside of the insulating material in an adjacent hole. The insulating layer and the electrically conductive layer can be further extended to the backside of the dies if desired. The dies are separated from each other and can be assembled in a stack and/or surface mounted to a substrate.

Claims

1. A method for assembling a stack of integrated circuit dies, comprising:

making holes through a wafer having a plurality of integrated circuit dies in which the dies include pads thereon connected to integrated circuits in the dies, said holes being placed between the dies and adjacent the pads;

placing a layer of insulating material over the wafer and in the outer periphery of the holes;

adding an electrically conductive connection between the top of each pad and the inside of the insulating material in an adjacent hole;

separating the plurality of dies from each other along lines extending through the holes between the dies; and

connecting a plurality of dies by an electrical interconnection between the electrically conductive connections on the inside of the cut holes of the dies.

2. The method of claim 1 further including connecting a die to a substrate by an electrical interconnection to the electrically conductive connection on the inside of the cut holes of the die.

3. The method of claim 1 wherein the holes are placed between pads on adjacent dies.

4. The method of claim 1 wherein scribe lines are positioned on the wafer between adjacent dies and the holes are placed on the scribe lines.

5. The method of claim 1 further including adding a dielectric layer between the top of a lower die and the bottom of an adjacent upper die after the dies are electrically interconnected.

6. A method of assembling a stack of integrated circuit dies, comprising:

making holes through a wafer having a plurality of integrated circuit dies in which the dies include pads thereon connected to integrated circuits in the dies, said holes being placed between the dies and adjacent the pads;

placing a layer of insulating material over the wafer and in the outer periphery of the holes;

removing the insulating material from the top of the pads;

adding an electrically conductive connection between the top of each pad and the inside of the insulating material in said adjacent hole;

separating the plurality of dies from each

other along lines passing through holes between the dies; and

connecting a plurality of dies by an electrical interconnection between the electrically conductive connections on the inside of the cut holes of the dies.

7. A method for assembling a stack of integrated circuit dies, comprising:

making holes through a wafer having a plurality of integrated circuit dies in which the dies include pads thereon connected to integrated circuits in the dies, said holes being placed between the dies and adjacent the pads;

placing a layer of insulating material over the wafer, in the outer periphery of the holes, and beneath the wafer along its backside;

adding an electrically conductive connection between the top of each pad, the inside of the insulating material in an adjacent hole, and the bottom of the insulating layer beneath the wafer so that the pads are electrically interconnected to conductors beneath the wafer; and

separating the plurality of dies from each other along lines extending through the holes between the dies.

8. The method of claim 7 wherein the holes are

placed between pads on adjacent dies.

9. The method of claim 7 wherein scribe lines are positioned on the wafer between adjacent dies and the holes are placed on the scribe lines.

10. The method of claim 7 further including connecting a plurality of dies by an electrical interconnection between the electrically conductive connections on the inside of the cut holes of the dies.

11. The method of claim 7 further including connecting a die to a substrate by an electrical interconnection to the electrically conductive connection on the bottom of the die.

12. The method of claim 7 further including connecting a plurality of dies by an electrical interconnection between the pads on the top of a first die and the conductors on the bottom of a second die.

13. The method of claim 12 further including adding a dielectric layer between the top of a first die and the bottom of an adjacent second die after the dies are electrically interconnected.

14. The method of claim 12 further including connecting electrically conductive bumps to the pads on the top of a die.

15. The method of claim 12 further including connecting electrically conductive bumps to the conductors on the bottom of a die.

16. The method of claim 15 wherein the electrically conductive bumps form an array pattern.

17. The method of claim 15 wherein the electrically conductive bumps are metals selected from the group consisting of solder, gold, and tin-lead alloys.

18. The method of claim 15 wherein the electrically conductive bumps are electrically conductive adhesives.

19. A method of assembling a stack of integrated circuit dies, comprising:

making holes through a wafer having a plurality of integrated circuit dies in which the dies include pads thereon connected to integrated circuits in the dies, said holes being placed between the dies and adjacent the pads;

placing a layer of insulating material over the wafer, in the outer periphery of the holes, and beneath the wafer;

removing the insulating material from the top of the pads;

adding an electrically conductive connection between the top of each pad, the inside of the insulating material in an adjacent hole, and the bottom of the insulating layer beneath the wafer so that the pads are electrically interconnected to conductors beneath the wafer; and

separating the plurality of dies from each other along lines passing through holes between the dies.

20. The method of claim 19 further including connecting a plurality of dies by an electrical interconnection between the pads on the top of a first die and the conductors on the bottom of a second die.