CMOS transfer switch free from malfunction on noise signal

• US 4,985,647 A
• Filed: 06/21/1989
• Issued: 01/15/1991
• Est. Priority Date: 06/21/1988
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kawada, Shigeru
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Wambach, M.
• Application Number:
  US07/369,532
• Time in Patent Office: 573 Days
• Field of Search: 307/542, 307/547-549, 307/242-243, 307/571-573, 307/443, 307/449, 307/463
• US Class Current: 326/113
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An analog switch comprises first and second FET switches connected in series between input and output terminals through a first interconnection point, a third FET switch connected between the first interconnection point and one of power terminals, fourth and fifth FET switches connected in series between input and output terminals through a second interconnection point and a sixth FET switch connected between the second interconnection point and the other of the power terminals, whereby the first, second and sixth FET switches are simultaneously turns on or off in a manner that their operating conditions are kept in phase opposite to the third, fourth and fifth FET switches.

Claims

1. An analog switch circuit comprising a control signal generator producing a control signal and an inverted control signal formed by inverting said control signal;

and input terminal receiving an input signal;

an output terminal;

first and second transistors of one conductivity type having gate electrodes and forming a first series-connection connected between said input terminal and said output terminal to turn on/off in response to said control signal mutually applied to said gate electrodes, thereby controlling a transfer of said input signal between said input and output terminals;

a third transistor connected between an interconnection node of said first and second transistors and one of a ground potential terminal and a power supply potential terminal and having a gate electrode receiving said control signal to perform an on/off operation which is opposite to the on/off operation of said first and second transistors in response to said control signal;

fourth and fifth transistors of the conductivity type opposite to said one conductivity type and having gate electrodes and forming a second series connection connected between said input and output terminals to turn on/off in response to said inverted control signal, said inverted control signal being mutually applied to the gate electrodes of said fourth and fifth transistors, thereby controlling a transfer of said input signal between said input and output terminals in synchronism with said first and second transistors; and

a sixth transistor connected between an interconnection node of said fourth and fifth transistors and another of said ground potential terminal and said power supply potential terminal to perform an on/off operation which is opposite to the on/of operation of said fourth and fifth transistors in response to said control signal.

2. An analog switch circuit as claimed in claim 1, wherein said third transistor is of said opposite conductivity type and is connected between said interconnection node of said first and second transistors and said ground potential terminal and said sixth transistor is of said one conductivity type and is connected between said interconnection node of said fourth and fifth transistors and said power supply potential terminal.

3. An analog switch circuit as claimed in claim 2, wherein said control signal is applied to said gate electrodes of said first, second and third transistors and said inverted control signal is applied to said gate electrodes of said fourth, fifth and sixth transistors.

4. An analog switch circuit as claimed in claim 1, wherein said third transistor is of said one conductivity type and is connected between said interconnection node of said first and second transistors and said power supply potential terminal and said sixth transistor is of said opposite conductivity type and is connected between said interconnection node of said fourth and fifth transistors and said ground potential terminal.

5. An analog switch circuit as claimed in claim 4, wherein said control signal is applied to said gate electrodes of said first, second and sixth transistors and said inverted control signal is applied to said gate electrodes of said third, fourth, and fifth transistors.

6. A switch circuit comprising:

an input terminal;

an output terminal;

first and second power terminals for supplying a power therefrom;

first and second switches connected in series between said input and output terminals through a first interconnection point;

a first control means for controlling said first and second switches to simultaneously turn said first and second switches on or off;

a third switch connected between said first interconnection point and one of said first and second power terminals;

a second control means for controlling said third switch so as to turn said third switch on or off in a manner that an on or off condition of said third switch is opposite to that of said first and second switches;

fourth and fifth switches connected in series between said input and output terminals through a second interconnection point;

a third control means for controlling said fourth and fifth switches to simultaneously turn said fourth and fifth switches on or off in a manner that on or off conditions of said fourth and fifth switches are the same as those of said first and second switches;

a sixth switch connected between said second interconnection point and another of said first and second power terminals; and

a fourth control means for controlling said sixth switch to turn said sixth switch on or off in a manner that an on or off condition of said sixth switch is opposite to that of said first and second switch.

7. A switch circuit as claimed in claim 6, wherein said first, second and sixth switches are field effect transistors of one channel type, while said third, fourth and fifth switches are field effect transistors of the other channel type.

8. A switch circuit as claimed in claim 7, wherein said first, second and third switches are controlled by a first control signal and said fourth, fifth and sixth switches are controlled by a second control signal which is opposite in phase to said first control signal.

9. A switch circuit as claimed in claim 6, wherein said first, second and third switches are field effect transistors of one channel type, while said fourth, fifth and sixth switches are field effect transistors of the other channel type.

10. A switch circuit as claimed in claim 9, wherein said first, second and sixth switches are controlled by a first control signal, and said third, fourth and fifth switches are controlled by a second control signal which is opposite in phase to said first control signal.