Method for forming a recessed contact bipolar transistor and field effect transistor

• US 4,985,744 A
• Filed: 09/21/1989
• Issued: 01/15/1991
• Est. Priority Date: 01/29/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Spratt, David B., Eklund, Robert H., Zorinsky, Eldon J., Virkus, Robert L.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/411,208
• Time in Patent Office: 481 Days
• Field of Search: 357/43, 357/23.9, 357/34, 357/55
• US Class Current: 257/370
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors

Abstract

Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.

Claims

1. An integrated circuit having a bipolar transistor and a field effect transistor, comprising:

a collector region of a first conductivity type formed in a first portion of a semiconductor substrate;

a base region of a second conductivity type formed in an upper portion of said collector region;

an emitter region of said first conductivity type formed in a semiconductor layer overlying said base region;

a gate electrode formed in said semiconductor layer overlying a second portion of said semiconductor substrate and defining the source to drain path of said field effect transistor;

a first recess extending through at least a portion of said base region and having at least one wall adjacent to one side of said emitter region;

a second recess extending through at least a portion of said base region and having another wall adjacent to another side of said emitter region;

a base contact region doped to said second conductivity type, formed in said first recess in said base region and spaced from said at least one wall;

a collector contact region doped to said first conductivity type formed in said second recess in said base region and spaced from said another wall; and

said collector contact region being spaced from said another wall by a distance greater than that of the distance said base contact region is spaced from said at least one wall.

2. The integrated circuit of claim 1, further comprising a sidewall insulator formed on said at least one wall.

3. The integrated circuit of claim 2, wherein said sidewall insulator comprises oxide.

4. The integrated circuit of claim 3 wherein said base contact region is aligned with said sidewall insulator.

5. The integrated circuit of claim 1, further comprising a second gate electrode formed in said semiconductor layer overlying a third portion of said semiconductor substrate and defining a second source to drain path of a second field effect transistor.