BiCMOS process and process for forming bipolar transistors on wafers also containing FETs

• US 4,987,089 A
• Filed: 07/23/1990
• Issued: 01/22/1991
• Est. Priority Date: 07/23/1990
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roberts, Ceredig
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/556,907
• Time in Patent Office: 183 Days
• Field of Search: 437/34, 437/46, 437/193, 437/31, 437/29, 437/59, 437/162, 437/152, 437/155, 437/56, 437/57, 437/186, 148/DIG. 9, 148/DIG. 82, 148/DIG. 105, 357/43
• US Class Current: 438/202
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: Y10S 148/009 Bi-MOS
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

A process for fabricating integrated circuits containing bipolar transistors in semiconductor wafers comprising the following steps:

forming a well and an upper insulating layer on a semiconductor wafer;

selectively patterning and doping a bipolar transistor base implant region into the well;

selectively patterning a layer of conductive material atop the insulating layer, the conductive material layer selectively exposing a first area of the base implant region and covering other areas of the base implant region, the conductive material layer having at least one first edge which at least in part defines the exposed first area;

doping through the exposed first area to form an emitter implant region within the base implant region, the conductive material layer masking without photoresist the other covered areas of the base implant region during doping of the exposed first area; then patterning the layer of conductive material to expose a second area of the base implant region and to form gates of MOS transistors elsewhere in the integrated circuits, the patterning to expose the second area defining at least one second conductive material edge atop the base implant region;

masking the first area and exposing the second area with photoresist; and

doping through the exposed second area to form a base contact.

Claims

1. A process for fabricating BiCMOS integrated circuits in p-type semiconductor wafers comprising the following steps:

forming a p-well, an n-well, and overlying field and gate insulating layers in a p-type wafer;

defining a first portion in the p-well for formation of an n-channel MOS transistor, a second portion in an n-well for formation of a p-channel MOS transistor, a third portion in an n-well for formation of a bipolar npn transistor, and a fourth portion in the n-well containing the third portion for formation of a collector contact in such n-well;

selectively patterning and doping a p-type base implant into the third portion;

selectively patterning a layer of conductive material atop the field and gate insulating layers to define a gate and exposed source and drain areas of the n-channel MOS transistor in the first portion, to cover the second portion, to selectively expose an area of the p-implanted third portion and to cover remaining areas of the p-implanted third portion, and to selectively expose the fourth portion;

doping exposed areas with n-type dopant material to a selected first concentration to form lightly doped drain regions in the p-well and the p-implanted third portion, the layer of conductive material masking without use of photoresist the second portion and covered areas of the third portion from implantation of n-type dopant material during the first concentration doping;

forming insulating spacers on exposed edges of the patterned conductive material to overlie at least the first and third portions and cover portions of the lightly doped drain regions therein;

doping exposed areas with n-type dopant material to a selected second concentration which is greater than the first concentration to form a source and a drain in the first portion, an emitter in the p-implanted third portion, and a collector contact region in the fourth portion, the layer of conductive material masking without use of photoresist the second portion and covered areas of the third portion from implantation of n-type dopant material during the second concentration doping;

selectively patterning with photoresist to define a gate and exposed source and drain areas of the p-channel MOS transistor in the second portion, to cover the emitter in the p-implanted third portion and expose a base contact region in the p-implanted third portion, to cover the collector contact region of the fourth portion, and to cover the first portion; and

doping exposed areas with p-type dopant material to a selected third concentration to form a source and a drain in the second portion and a base contact region in the p-implanted third portion.

2. The process for fabricating BiCMOS integrated circuits of claim 1 wherein the recited conductive material is everywhere conductively doped polysilicon.

3. The process for fabricating BiCMOS integrated circuits of claim 1 wherein the p-channel MOS transistor and bipolar transistor are formed in a single n-well.

4. The process for fabricating BiCMOS integrated circuits of claim 1 wherein,

the recited conductive material is everywhere conductively doped polysilicon;

and

the p-channel MOS transistor and bipolar transistor are formed in a single n-well.

5. The process for fabricating BiCMOS integrated circuits of claim 1 further comprising doping multiple discrete contacts for the emitter and for the base contacts.

6. The process for fabricating BiCMOS integrated circuits of claim 5 wherein,

the recited conductive material is everywhere conductively doped polysilicon;

and

the p-channel MOS transistor and bipolar transistor are formed in a single n-well.

7. A process for fabricating BiCMOS integrated circuits in n-type semiconductor wafers comprising the following steps:

forming an n-well, a p-well, and overlying field and gate insulating layers on an n-type wafer;

defining a first portion in the n-well for formation of a p-channel MOS transistor, a second portion in a p-well for formation of an n-channel MOS transistor, a third portion in a p-well for formation of a bipolar PNP transistor, and a fourth portion in the p-well containing the third portion for formation of a collector contact in such p-well;

selectively patterning and doping an n-type base implant into the third portion;

selectively patterning a layer of conductive material atop the field and gate insulating layers to define a gate and exposed source and drain areas of the p-channel MOS transistor in the first portion, to cover the second portion, to selectively expose an area of the n-implanted third portion and cover remaining areas of the n-implanted third portion, and to selectively expose the fourth portion;

doping exposed areas with p-type dopant material to a selected first concentration to form a source and a drain in the first portion, an emitter in the n-implanted third portion, and a collector contact region in the fourth portion;

selectively patterning with photoresist to define a gate and exposed source and drain areas of the n-channel MOS transistor in the second portion, to cover the emitter in the p-implanted third portion and expose a base contact region in the p-implanted third portion, to cover the collector contact region of the fourth portion, and to cover the first portion;

doping exposed areas with n-type dopant material to a selected second concentration to form lightly doped drain regions in the second portion;

forming insulating spacers on exposed edges of the patterned conductive material overlying at least the second portion to cover portions of the lightly doped drain regions therein; and

doping exposed areas with n-type dopant material to a selected third concentration which is greater than the second concentration to form a source and a drain in the second portion and a base contact region in the p-implanted third portion.

8. The process for fabricating BiCMOS integrated circuits of claim 7 wherein the recited conductive material is everywhere conductively doped polysilicon.

9. The process for fabricating BiCMOS integrated circuits of claim 7 wherein the n-channel MOS transistor and bipolar transistor are formed in a single p-well.

10. The process for fabricating BiCMOS integrated circuits of claim 7 wherein,

the recited conductive material is everywhere conductively doped polysilicon;

and

the n-channel MOS transistor and bipolar transistor are formed in a single p-well.

11. The process for fabricating BiCMOS integrated circuits of claim 7 further comprising doping multiple discrete contacts for the emitter and for the base contacts.

12. The process for fabricating BiCMOS integrated circuits of claim 11 wherein,

the recited conductive material is everywhere conductively doped polysilicon;

and

the n-channel MOS transistor and bipolar transistor are formed in a single p-well.

13. A process for fabricating integrated circuits containing bipolar transistors in semiconductor wafers comprising the following steps:

forming a well and an upper insulating layer on a semiconductor wafer;

selectively patterning and doping a bipolar transistor base implant region into the well;

selectively patterning a layer of conductive material atop the insulating layer, the conductive material layer selectively exposing a first area of the base implant region and covering other areas of the base implant region, the conductive material layer having at least one first edge which at least in part defines the exposed first area;

doping through the exposed first area to form an emitter implant region within the base implant region, the conductive material layer masking without photoresist the other covered areas of the base implant region during doping of the exposed first area;

patterning the layer of conductive material to expose a second area of the base implant region and to form gates of MOS transistors elsewhere in the integrated circuits, the patterning to expose the second area defining at least one second conductive material edge atop the base implant region and also masking the first area with photoresist; and

doping through the exposed second area to form a base contact.

14. The process for fabricating integrated circuits of claim 13 wherein the recited conductive material is everywhere conductively doped polysilicon.

15. The process for fabricating integrated circuits of claim 13 wherein the step of selectively patterning a layer of conductive material atop the insulating layer comprises patterning such layer to provide and exposed third area in the well which is spaced from the base implant region;

wherein the step of doping through the exposed first area also simultaneously comprises doping through the exposed third region to form a collector contact; and

wherein the step of patterning the layer of conductive material to expose a second area of the base implant region also comprises masking the third area with photoresist.

16. The process for fabricating integrated circuits of claim 15 wherein the recited conductive material is everywhere conductively doped polysilicon.