Semiconductor integrated circuit device having an improved common wiring arrangement

• US 4,987,326 A
• Filed: 04/28/1989
• Issued: 01/22/1991
• Est. Priority Date: 04/30/1988
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Satoh, Yasuo, Kobayashi, Tohru
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/344,669
• Time in Patent Office: 634 Days
• Field of Search: 307/443, 307/455, 307/465-467, 307/303.1, 364/491, 357/45
• US Class Current: 326/43
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/11801 using bipolar technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays

Abstract

In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate circuit and a branch node corresponding thereto are in the proximity of one another. A terminal resistor is interposed between a first end of the first common combined wiring and a power source voltage or ground potential of the circuit, and the second end of the first common combined wiring is coupled to a second common combined wiring connecting the input terminals of the logic gate circuits on the input side.

Claims

1. A semiconductor integrated circuit device comprising:

a first logic gate cell group;

a first common wiring for connecting an output terminal of each logic gate cell in said first logic gate cell group in order to connect said output terminals with one another, wherein said first common wiring has a first end and a second end, and wherein said output terminals of each of said logic gate cells in said first logic gate cell are coupled to said first common wiring between said first and said second ends;

a terminal resistor disposed inside a logic gate cell connected to the first end of said first common wiring, for setting the output level used commonly for said logic gate cells in said first logic gate cell group;

a second logic gate cell group; and

a second common wiring coupled to said second end of said first common wiring for connecting an input terminal of each of said logic gate cells in said second logic gate cell group to the second end of said first common wiring.

2. A semiconductor integrated circuit device according to claim 1, wherein each of said logic gate cells includes an emitter coupled logic circuit and an emitter output transistor whose emitter is connected to the output terminal of said logic gate cell.

3. A semiconductor integrated circuit device according to claim 2, wherein said terminal resistor is connected as an emitter resistor to said emitter output transistor of said logic gate cell connected to the first end of said first common wiring among said logic gate cells of said first logic gate cell group, and said emitter output transistors of the other of said logic gate cells are of an open emitter type. PG,43

4. A semiconductor integrated circuit device according to claim 3, wherein said semiconductor integrated circuit device is a gate array integrated circuit device and said first and second common wirings are coupled to each other through a logic gate cell connected between said first logic gate cell group and said second logic gate cell group.