Computer capable of accessing a memory by supplying an address having a length shorter than that of a required address for the memory

• US 4,987,537 A
• Filed: 05/31/1988
• Issued: 01/22/1991
• Est. Priority Date: 05/31/1987
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kawata, Kazuhide
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/200,207
• Time in Patent Office: 966 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/212
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A computer comprises an instruction memory storing therein instruction codes and including a plurality of divided address spaces, and a CPU receiving an instruction read out of the instruction memory for executing the read-out instruction and outputting an address data for an instruction code to be next executed to the instruction memory. In addition, there is provided a space code memory storing respective codes indicative of the divided address spaces within the instruction memory for respective instruction codes stored in the instruction memory, for generating an address space code for an instruction to be executed next to an instruction code designated by the address given to the instruction memory. A flipflop is provided to latch the address space code generated by the space code memory so as to supply the latched address space code to the instruction memory after one instruction execution time, so that the instruction memory is address-designated by a combination of the address data outputted from the CPU and the address space code delayed by the flipflop.

Claims

1. A computer comprising an instruction memory storing therein instruction codes an having its entire memory region divided into a plurality of non-overlapping memory address spaces, a CPU receiving a received instruction code read out of said instruction memory for executing said received instruction code and outputting to said instruction memory address data for an instruction code to be executed next after said received instruction code, said address data being composed to designate one memory location included in each of said memory address spaces, a space code memory storing respective address space codes each indicative of one of said address spaces within said instruction memory, and delay means for delaying said address space code outputted by said space code memory by one instruction execution time to produce a delayed address space code, said delayed address space code being combined with said address data outputted by said CPU so as to form a complete address for accessing said instruction memory and said complete address being supplied to said instruction memory and said space code memory, so that an instruction code is read out to said CPU from a location of said instruction memory designated by said supplied complete address, and an address space code indicative of a memory address space including a memory location storing an instruction to be executed next after said read-out instruction code is read out from said space code memory so as to be outputted to said delay means.

2. The computer as claimed in claim 1 wherein said space code memory stores a memory address space code for each instruction code at an address corresponding to an address of said instruction memory storing an instruction code to be executed just before execution of said each instruction code, so that, when the same address "X" is applied from said CPU to said instruction memory and said space code memory, said instruction memory reads out an instruction "Y" stored at the address "X" within said instruction memory, and said space code memory reads a space code stored at the address "X" within said space code memory, said read-out space code being indicative of an address space within said instruction memory including an address "X+1" storing an instruction "Y+1" to be executed next to the instruction "Y" stored at the address "X".

3. The computer as claimed in claim 1 wherein said delay means includes a flipflop having a D input connected to receive a signal indicative of said address space code from said space code memory and a Q output connected to the address input of said instruction memory and space code memory, said flipflop responding to clock signals so as to latch said signal indicative of said address space code from said space code memory.

4. The computer as claim in claim 3 wherein said clock signals and instruction cycles are timed to each other such that each of said clock signals has already assumed a high level when each of instruction cycles starts, and then reaches a low level around a middle of each instruction cycle, and then returns to said high level sufficiently before an end of each instruction cycle, said CPU, said instruction memory, said space code memory, and said flipflop interacting so that at the rising edge of each clock signal, said flipflop latches said signal indicative of said address space code outputted from said space code memory, and at the falling edge of each clock signal, said instruction memory outputs an instruction code corresponding to said supplied complete address, and on the other hand, at the start of each instruction cycle, said CPU executes said instruction code outputted from said instruction memory and said space code memory outputs said address space code to said flipflop.