High speed ECL/CML to TTL translator circuit

• US 4,988,898 A
• Filed: 05/15/1989
• Issued: 01/29/1991
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Jansson, Lars G.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US07/352,169
• Time in Patent Office: 624 Days
• Field of Search: 307/455, 307/456, 307/457, 307/475, 307/443, 307/355, 307/358, 307/360, 307/363, 307/270, 307/264, 307/247.1, 307/544, 307/546, 307/547, 307/549, 307/551, 307/553 , 307/558, 307/559, 307/560, 307/567, 323/312, 323/315, 323/316, 323/317
• US Class Current: 326/78
• CPC Class Codes: H03K 19/013 in bipolar transistor circuits
• CPC Class Codes: H03K 19/01806 Interface arrangements
• CPC Class Codes: H03K 19/01812 with at least one differential stage

Abstract

An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region. The circuit functions of reference voltage level shifting and of operating region translating are thereby separately performed by separate components. The TTL gate input is a phase splitter transistor element. A resistor pulldown discharges the phase splitter transistor element. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp. More generally, an overdrive and anti-saturation clamp circuit provides high speed switching of the phase splitter or other TTL switching transistor element.

Claims

1. An ECL/CML to TTL translator circuit for coupling the output of ECL/CML gate to the input of a TTL gate, said ECL/CML gate operating with reference to a specified reference voltage level and in the non-saturation operating region, comprising:

a reference voltage level shifting current mirror circuit means having a non-current switching constant current first branch circuit and a second branch circuit coupled in current mirror configuration with the first branch circuit, said second branch circuit being coupled to the output of the ECL/CML gate and being constructed for shifting the reference voltage level at the ECL/CML gate output and for delivering a reference voltage level shifted output signal at a second branch circuit output node;

and an operating region translating emitter follower output buffer circuit having an emitter follower transistor element coupled in emitter follower configuration with a base node coupled to the second branch circuit output node of the current mirror circuit means to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation operating region;

said circuit functions of reference voltage level shifting and of operating region translating being thereby separately performed by separate components respectively of said current mirror circuit means and said emitter follower output buffer circuit.

2. The translator circuit of claim 1 wherein the emitter follower output buffer circuit comprises resistor pulldown means coupled to the TTL gate input for resistive discharge of a transistor element of the TTL gate input.

3. An ECL/CML to TTL translator circuit for coupling the output of an ECL/CML gate to the input of a TTL gate, said ECL/CML gate operating with reference to a first power rail higher reference voltage level and said TTL gate operating with reference to a second power rail lower reference voltage level, said translator circuit comprising:

a reference voltage level shifting constant current circuit comprising a first current mirror branch circuit and first current mirror transistor element operatively coupled between the higher reference voltage level and the lower reference voltage level for generating a constant reference current, a second current mirror branch circuit and second current mirror transistor element operatively coupled between the ECL/CML gate output and the lower reference voltage level, said second current mirror transistor element being coupled in current mirror configuration with the first current mirror transistor element for mirroring the constant reference current at the output of the ECL/CML gate, and level shifting resistance means in the second current mirror branch circuit for shifting the reference voltage level of an output signal from the ECL/CML gate output from the higher to the lower reference voltage level at a collector node of the second current mirror transistor element, said collector node providing a reference voltage level shifted output.

4. The translator circuit of claim 3 wherein the ECL/CML gate comprises transistor elements operating in the non-saturation operating region and wherein the TTL gate comprises transistor elements operating in the saturation operating region, and further comprising:

an operating region translating circuit comprising an emitter follower output buffer circuit operating in the non-saturation operating region and operatively coupled to receive base drive from the reference voltage level shifted output and to drive the input of the TTL gate in the saturation operating region, thereby separating the circuit functions of reference voltage level shifting and of operating region translating into separate circuit components of the translator circuit.

5. The translator circuit of claim 4 wherein the emitter follower output buffer circuit comprises resistor pulldown means operatively coupled between the TTL gate input and the lower reference voltage level for discharging a transistor element of the TTL gate through the resistor pulldown means.

6. The translator circuit of claim 5 wherein the TTL gate comprises a phase splitter transistor element coupled to receive base drive from the emitter follower output buffer circuit, said resistor pulldown means being coupled between the base node of the phase splitter transistor element and the lower reference voltage level.

7. The translator circuit of claim 6 further comprising a base drive clamp circuit operatively coupled between the collector node of the phase splitter transistor element and the base node of the emitter follower output buffer circuit for clamping operation of the phase splitter transistor element in the soft or threshold saturation operating region.

8. The translator circuit of claim 7 wherein the base drive clamp circuit comprises a resistor and a V_be diode junction coupled in series.

9. The translator circuit of claim 7 wherein the base drive clamp circuit comprises a Schottky diode junction and a V_be diode junction in series.

10. The translator circuit of claim 4 wherein the TTL gate input comprises a TTL transistor element coupled to receive base drive from the emitter follower output buffer circuit, and further comprising a base drive clamp circuit coupled between a collector node of the TTL transistor element and a base node of the emitter follower output buffer circuit for clamping operation of the TTL transistor element in the soft or threshold saturation operating region.

11. The translating circuit of claim 10 wherein the base drive clamp circuit comprises a resistor and a V_be diode junction coupled in series.

12. An ECL/CML to TTL translator circuit for coupling the output of an ECL/CML gate to the input of a TTL gate, said ECL/CML gate operating with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region of the operating characteristics of the ECL/CML gate transistor elements, said TTL gate operating with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region of the operating characteristics of the TTL gate transistor elements, said ECL/CML and TTL gates having respective inputs and outputs switching between high and low potential levels for transmitting data, said translator circuit comprising:

a reference voltage level shifting current mirror circuit having a first constant current source branch circuit coupled between the higher and lower reference voltage levels without direct connection to the ECL/CML gate output, for generating a substantially constant reference current between the higher and lower reference voltage levels and maintaining said constant reference current during switching of the ECL/CML gate input and output, said first constant current source branch circuit comprising a first current mirror transistor element;

said reference voltage level shifting current mirror circuit comprising a second constant current source branch circuit operatively coupled between the ECL/CML gate output and the lower reference voltage level, said second constant current source branch circuit comprising a second current mirror transistor element operatively coupled in current mirror configuration with the first current mirror transistor element for mirroring the substantially constant reference current in the second constant current source branch circuit and for maintaining said mirrored constant reference current during switching of the ECL/CML gate input and output;

and level shifting resistance means coupled to the collector node of the second current mirror transistor element in the second constant current source branch circuit, for shifting the reference voltage level at the collector node of the second current mirror transistor element from the higher reference voltage level to the lower reference voltage level for providing a reference voltage level shifted output at said collector node.

13. The translator circuit of claim 12 further comprising:

an operating region translating circuit comprising an emitter follower transistor element output buffer circuit coupled to receive base drive from the collector node of the second current mirror transistor element and having an emitter node coupled to the TTL gate input for driving the input of the TTL gate in the saturation operating region.

14. The translator circuit of claim 13 wherein the TTL gate input is coupled to the lower reference voltage level through resistor pulldown means for discharging a transistor element of the TTL gate to said lower reference voltage level through the resistor pulldown means.

15. The translator circuit of claim 14 wherein the TTL gate input comprises a phase splitter transistor element coupled to receive base drive from an emitter node of the emitter follower transistor element output buffer circuit, said resistor pulldown means being coupled between the base node of the phase splitter transistor element and the lower reference voltage level.

16. The translator circuit of claim 15 further comprising a base drive limiting resistor element coupled between an emitter node of the emitter follower transistor element output buffer circuit and the phase splitter transistor element.

17. The translator circuit of claim 15 comprising a base drive clamp circuit coupled between a base node of the emitter follower transistor element output buffer circuit and the collector node of the TTL gate phase splitter transistor element for clamping operation of the phase splitter transistor element in the soft or threshold saturation operating region.

18. The ECL/CML to TTL translator circuit of claim 12 wherein the first constant current source branch circuit comprises a standard reference resistance means having resistance substantially equal to the reference voltage level shifting resistance means in the second constant current source branch circuit, and wherein a standard reference voltage drop across the standard reference resistance means is established by a diode stack from the lower reference voltage level.

19. The translator circuit of claim 18 wherein the diode stack comprises at least one base collector shorted (BCS) transistor element and wherein said BCS transistor element also comprises the first current mirror transistor element.

20. The translator circuit of claim 18 further comprising a tail current source for the ECL/CML gate and wherein the first constant current source branch circuit is coupled to drive the tail current source for the ECL/CML gate, said diode stack establishing a tail current source voltage V_CS.

21. In an ECL/CML to TTL translator circuit for coupling the output of an ECL/CML gate to the input of a TTL gate, said TTL gate input comprising a TTL input transistor element, said ECL/CML gate operating with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region of the operating characteristics of the ECL/CML gate transistor elements, said TTL gate operating with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region of the operating characteristics of the TTL gate transistor elements, said translator circuit including a reference voltage level shifting current mirror circuit having first and second current mirror branch circuits with respective first and second current mirror transistor elements operatively coupled in current mirror configuration with a level shifting resistor element in the second current mirror branch circuit, the collector node of the second current mirror transistor element providing a reference voltage level shifted output of the current mirror circuit, the improvement comprising:

an emitter follower transistor element output buffer operating in the non-saturation operating region and having a base node coupled to said second current mirror transistor element collector node, said emitter follower transistor element output buffer being coupled to the input of a TTL gate for driving a TTL gate transistor element in the saturation operating region, said emitter follower transistor element output buffer providing an operating region translating circuit thereby separating the functions of reference voltage level shifting and operating region translating in separate circuit components of the translating circuit, resistor pulldown means coupled between the TTL input transistor element and the lower reference voltage level for discharging the TTL input transistor element through the resistor pulldown means, and a base drive clamp circuit coupled between a collector node of the TTL input transistor element and the base node of the emitter follower transistor element output buffer to clamp the operation of the TTL input transistor element in the soft or threshold saturation operating region.

22. The transistor circuit of claim 21 wherein the base drive clamp circuit comprises a resistor and a V_be diode junction coupled in series.

23. The translator circuit of claim 21 wherein the base drive clamp circuit comprises a Schottky diode junction and a V_be diode junction coupled in series.

24. The translator circuit of claim 21 wherein the TTL input transistor element comprises a phase splitter transistor element.