Single bus graphics data processing pipeline with decentralized bus arbitration

• US 4,989,138 A
• Filed: 05/14/1990
• Issued: 01/29/1991
• Est. Priority Date: 09/02/1988
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Radochonski, Pierre A.
• Primary Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/522,508
• Time in Patent Office: 260 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/119
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus. When the sending stage determines from the state of the BUSY bit that the next stage is ready to receive input data, the sending stage acquires control of the bus and sends the input data thereon to the next stage.

Claims

1. A data processing system implementing a sequence of data processing operations, comprising:

a bus for conveying data, an address and a bus arbitration signal;

a plurality of data processing stages connected to said bus for receiving the data, address and arbitration signal conveyed by the bus,

each stage comprising processing means for performing a separate data processing operation of said sequence by producing output data and addresses in response to input data received on said bus, output data produced by each of said stages other than a stage performing a last operation of said sequence being provided as input data to another of said stages via said bus, and,

each stage further comprising bus master means responsive to requests from said processing means of the same said stage for monitoring said bus arbitration signal to determine when said bus is not in use by another stage, and for setting said bus arbitration signal to indicate said bus is in use wherein said bus arbitration signal is transmitted on said bus for reception by another of said data processing stages via said bus, transmitting output data and addresses on said bus, and thereafter setting said bus arbitration signal to indicate said bus is not in use, such that said bus master means in said plurality of data processing stages provides decentralized bus arbitration for use of said bus.

2. The data processing system in accordance with claim 1 further comprising an addressable memory connected to said bus for reading out data onto said bus when read accessed, wherein the bus master means of at least one of said stages read accesses said addressable memory via said bus to obtain input data for said processing means.

3. The data processing system in accordance with claim 1 further comprising an addressable memory connected to said bus for storing data conveyed on said bus when write accessed and reading out data onto said bus when read accessed, wherein said bus master means of at least one of said stages read and write accesses said addressable memory via said bus to obtain input data for said processing means and to store in said memory output data produced by said processing means.

4. The data processing system in accordance with claim 1 further comprising an addressable memory connected to said bus for storing data conveyed on said bus when write accessed and for reading out data onto said bus when read accessed, wherein said bus master means of at least two of said stages read and write access said addressable memory via said bus to obtain input data for said processing means and to store in said memory output data produced by said processing means.

5. The data processing system in accordance with claim 1 wherein at least one of said stages includes means responsive to a particular address on said bus for placing on said bus data indicating whether said at least one stage is ready to receive input data.

6. The data processing system in accordance with claim 1 wherein at least one of said stages comprises means for placing a particular address on said bus and wherein said another of said stages includes means responsive to said particular address on said bus for placing on said bus data indicating whether said another of said stages is ready to receive as input data output data produced by said at least one stage.

7. The data processing system in accordance with claim 1 wherein at least one of said stages further comprises:

means for storing input data transmitted on said bus when said input data is accompanied on said bus by a first particular address; and

means responsive to a second particular address transmitted on said bus, for placing on said bus data indicating whether said processing means has completed performing a computation.

8. A data processing system implementing a sequence of data processing operations, comprising:

a bus for concurrently conveying data, an address, and a bus arbitration signal;

an addressable memory connected to said bus for storing data conveyed on said bus and reading out data onto said bus;

a plurality of data processing stages connected in parallel to said bus and concurrently receiving the data, address and arbitration signal conveyed by the bus,

each stage comprising processing means for performing a separate data processing operation of said sequence by producing output data and addresses in response to input data received on said bus, output data produced by each of said stages other than a stage performing a last operation of said sequence of operations being provided as input data to another of said stages via said bus, and

each stage further comprising bus master means responsive to requests from said processing means for monitoring said bus arbitration signal to determine when said bus is not in use by another stage, for setting said bus arbitration signal to indicate said bus is in use wherein said bus arbitration signal is transmitted on said bus for reception by another of said data processing stages via said bus, and for transmitting output data and addresses on said bus while controlling said bus and thereafter setting said bus arbitration signal to relinquish control of the bus, such that said monitoring and setting of said bus arbitration signal provides decentralized bus arbitration, and wherein the bus master means of at least one of said stages read and write accesses said addressable memory via said bus to obtain input data for said processing means and to store output data produced by said processing means,

at least one of said stages further comprising means for placing a particular address on said bus, and

at least one other of said stages further comprising means responding to said particular address placed on said bus by placing data on said bus indicating whether said one other of said stages is ready to receive as input data output data produced by said at least one stage.