Method for coplanar integration of semiconductor ic devices
First Claim
1. A method for coplanar integration of semiconductor IC devices comprising:
- (a) providing segments having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having on a top surface thereof at least one of the items selected from the group consisting of circuits, circuit elements, sensors, and input/output connections;
(b) arranging said segments on the surface of a flotation liquid such that the top surfaces of each segment are substantially coplanar;
(c) allowing said segments to be pulled together so as to mate abutting edges of neighboring segments to form a superchip;
(d) forming solid microbridges between neighboring segments to mechanically secure said superchip; and
(e) forming electrical interconnections between neighboring segments so as to interconnect various of said circuits, circuit elements, sensors, and input/output connections.
1 Assignment
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Accused Products
Abstract
A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'"'"'). Each segment is provided with at least one edge (12) having an abutting portion (12a) capable of abutting against a similar edge of a neighboring segment. The segments are placed on the surface of a flotation liquid (20) and are allowed to be pulled together so as to mate abutting edges of neighboring segments, thereby forming superchips (10'"'"'). Microbridges (22) are formed between neighboring segments, such as by solidifying the flotation liquid, and interconnections (26) are formed between neighboring segments. In this manner, coplanar integration of semiconductor ICs is obtained, permitting mixed and normally incompatible circuit functions on one pseudomonolithic device as diverse as silicon and III-V digital circuits, III-V optoelectonic devices, static RAMs, charge coupled devices, III-V lasers, superconducting thin films, ferromagnetic non-volatile memories, high electron mobility transistors, and bubble memories, to name a few, to be integrated in any desired combination. The yieldable scale of integration of a given device technology is also greatly extended. The segments are brought together in a particulate-free fashion with high throughput and exacting reproducibility at low cost.
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Citations
42 Claims
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1. A method for coplanar integration of semiconductor IC devices comprising:
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(a) providing segments having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having on a top surface thereof at least one of the items selected from the group consisting of circuits, circuit elements, sensors, and input/output connections; (b) arranging said segments on the surface of a flotation liquid such that the top surfaces of each segment are substantially coplanar; (c) allowing said segments to be pulled together so as to mate abutting edges of neighboring segments to form a superchip; (d) forming solid microbridges between neighboring segments to mechanically secure said superchip; and (e) forming electrical interconnections between neighboring segments so as to interconnect various of said circuits, circuit elements, sensors, and input/output connections. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for coplanar integration of semiconductor IC devices comprising:
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(a) providing segments having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having thereon at least one of the items selected from the group consisting of circuits, circuit elements, and connectors; (b) arranging said segments on the surface of a flotation liquid; (c) allowing said segments to be pulled together so as to mate abutting edges of neighboring segments; (d) forming microbridges between neighboring segments by solidifying said flotation liquid; and (e) forming conductive interconnections between neighboring segments. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. A method for coplanar integration of semiconductor IC devices comprising:
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(a) providing segments having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having on a top surface thereof at least one of the items selected from the group consisting of circuits, circuit elements, sensors, and input/output connections; (b) forming wettable portions on said top surfaces which are made wettable to a flotation liquid; (c) placing said segments on a first surface such that said top surfaces of said segments are face up; (d) placing wetting drops of said flotation liquid such that said wettable portions of said top surface and said edges of each segment are wetted; (e) arranging a reference surface to contact said top of said segments in cowetted contact therewith; (f) urging said segments together so as to mate abutting edges of neighboring segments to form a superchip; (g) forming microbridges between neighboring segments to mechanically secure said superchip; and (h) forming electrical interconnections between neighboring segments so as to interconnect various of said of circuits, circuit elements, sensors, and input/output connections. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A method for coplanar integration of semiconductor IC devices comprising:
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(a) providing segments having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having on a top surface thereof at least one of the items selected from the group consisting of circuits, circuit elements, sensors, and input/output connections; (b) placing said segments on a reference surface such that said top surfaces of said segments are face down to ensure coplanarity of said top surfaces; (c) placing a flotation liquid such that spaces between neighboring segments are substantially filled therewith and said edges of said segments are wetted; (d) allowing said segments to be drawn together so as to mate abutting edges of neighboring segments to form a superchip; (e) forming microbridges between neighboring segments to mechanically secure said superchip; and (f) forming electrical interconnections between neighboring segments so as to interconnect various of said of circuits, circuit elements, sensors, and input/output connections. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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Specification