Logarithmic amplifier

• US 4,990,803 A
• Filed: 03/27/1989
• Issued: 02/05/1991
• Est. Priority Date: 03/27/1989
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Gilbert, Barrie
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US07/328,966
• Time in Patent Office: 680 Days
• Field of Search: 307/296.6, 307/491, 307/494, 307/492, 307/310, 330/297, 330/296, 330/138, 330/140, 330/289, 330/256, 328/144, 328/145, 328/168
• US Class Current: 327/351
• CPC Class Codes: H03G 7/001 without controlling loop H03G7/007, H03G7/02, H03G7/06 take precedence

Abstract

A multi-stage logarithmic converter of the "successive-detection" or "progressive-compression" type including circuitry providing an accurate, temperature-stabilized logarithmic transfer function. The gain stages are DC-coupled throughout, though each also employs a demodulator comprising a full-wave rectifier, allowing operation in both baseband and demodulating modes. The signal path is differential and is balanced, including the demodulators. Each gain stage is based on a differential amplifier, or "long-tail pair" operated in an open-loop mode and biased by a tail current generator which supplies a tail current that is both proportional to absolute temperature and compensated automatically for effects of finite transistor beta and base and emitter resistances. The demodulators are biased by a very low offset voltage which also is proportional to absolute temperature. The log intercept is temperature-stabilized by either employing a PTAT attenuator ahead of the complete amplification system or by introducing at the output node (a current summing junction) a current which varies with temperature in such a way as to offset intercept movement which otherwise would be generated.

Claims

1. A logarithmic converter for supplying in response to an instantaneous input signal an output signal representing a corresponding logarithmic value thereof, the performance of the converter being characterized at least in part by a log intercept value and by a log slope, and comprising:

a. a plurality of gain stages, each having

(i) a transistor amplifier which has an input and an output, and

(ii) a full-wave detector having an input and an output, the input of the full-wave detector being connected to receive the output of the transistor amplifier;

b. a first one of the amplifiers being connected to receive at its input the input signal;

c. each other amplifier being connected to receive at its input the output from another one of the amplifiers;

d. the full-wave detectors each supplying a current output and the current outputs of all of the detectors being summed to provide the converter'"'"'s output; and

e. stabilization means operatively associated with each amplifier to cause the gain of the amplifier to be substantially insensitive to temperature variations and variations in production tolerances of the amplifier transistors.

2. The logarithmic converter of claim 1, wherein the transistor amplifiers are differential amplifiers biased by a tail current and wherein the stabilization means includes means for generating a tail current for each amplifier, which tail current is substantially proportional to absolute temperature.

3. The logarithmic converter of claim 2 wherein the means for generating the tail current is adapted to provide a tail current which is a function of the current gain of the amplifier transistors and their intrinsic resistances.

4. The logarithmic converter of any of claims 1-3 further including means for compensating for the temperature dependence of the detector output currents, to stabilize the log intercept.

5. The logarithmic converter of claim 4 wherein the means for compensating includes an attenuator at the input of the first amplifier, said attenuator providing an attenuation factor which is proportional to absolute temperature.

6. The logarithmic converter of claim 4 wherein the means for compensating includes means for combining with the summed detector output currents a current which compensates for changes in the summed current with variations in temperature.