Non-volatile memory cell
First Claim
1. In a non-volatile memory cell array including a plurality of non-volatile memory cells which are formed at a surface of a semiconductor substrate and which each includes spaced source and drain zones formed in said surface, a trench provided in said surface adjacent the side of said drain zone facing away from the channel zone, a tunnel through dielectric layer disposed on said surface and covering at least the side walls of said trench, and a floating-gate electrode, as the memory electrode, disposed on said dielectric layer and extending into said trench;
- the improvement wherein;
said drain zone of at lest two of said non-volatile memory cells are disposed adjacent a single said trench and said floating-gate electrodes of said at lest two memory cells extend into said signal trench so that tunnel current can flow horizontally to the semiconductor surface between a respective said drain zone and the associated one of said floating-gate-electrodes.
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Accused Products
Abstract
The invention relates to an electrically erasable floating-gate memory cell (EEPROM) in which the Fowler-Nordheim tunnel effect is exploited for programming and erasing. In accordance with the invention, a trench adjacent to the side of the drain zone facing away from the channel zone and covered with a dielectric tunnel layer is provided in the semiconductor element, so that the floating-gate electrode extends into the trench in such a way that the tunnel current can flow horizontally to the semiconductor surface between the drain zone and the floating-gate electrode. This permits a reduction in the cell size and to higher integration densities. Preferably the floating gate electrodes of at least two cells extend into a single trench.
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Citations
10 Claims
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1. In a non-volatile memory cell array including a plurality of non-volatile memory cells which are formed at a surface of a semiconductor substrate and which each includes spaced source and drain zones formed in said surface, a trench provided in said surface adjacent the side of said drain zone facing away from the channel zone, a tunnel through dielectric layer disposed on said surface and covering at least the side walls of said trench, and a floating-gate electrode, as the memory electrode, disposed on said dielectric layer and extending into said trench;
- the improvement wherein;
said drain zone of at lest two of said non-volatile memory cells are disposed adjacent a single said trench and said floating-gate electrodes of said at lest two memory cells extend into said signal trench so that tunnel current can flow horizontally to the semiconductor surface between a respective said drain zone and the associated one of said floating-gate-electrodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- the improvement wherein;
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10. In a non-volatile memory cell array including at least first and second non-volatile memory cells formed on a semiconductor substrate and each including a floating-gate field effect transistor having spaced source and drain zones formed in a surface of said semiconductor substrate and defining a channel zone therebetween, and a floating-gate electrode, which serves as the memory electrode, arranged on a tunnel-through dielectric layer disposed on said surface of said semiconductor substrate;
- the improvement wherein;
a single trench is formed in said surface of said semiconductor element adjacent the side of the drain zone which faces away from the respective said channel zone of at least each of said first and second memory cells; said dielectric layer covers at least the side walls of said trench; and said floating gate electrode of each of said first and second memory cells extends along said dielectric layer into said trench and over respective portions of said side walls such that tunnel current can flow horizontally to the semiconductor surface between said drain zones and respectively associated said floating-gate electrodes.
- the improvement wherein;
Specification