Non-volatile memory cell

• US 4,990,979 A
• Filed: 04/27/1989
• Issued: 02/05/1991
• Est. Priority Date: 05/13/1988
• Status: Expired due to Fees

• Current Assignee: Eurosil Electronic GmbH
• Original Assignee: Eurosil Electronic GmbH
• Inventors: Otto, Joachim
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/350,722
• Time in Patent Office: 649 Days
• Field of Search: 357/23.6, 357/55, 365/185
• US Class Current: 257/321
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention relates to an electrically erasable floating-gate memory cell (EEPROM) in which the Fowler-Nordheim tunnel effect is exploited for programming and erasing. In accordance with the invention, a trench adjacent to the side of the drain zone facing away from the channel zone and covered with a dielectric tunnel layer is provided in the semiconductor element, so that the floating-gate electrode extends into the trench in such a way that the tunnel current can flow horizontally to the semiconductor surface between the drain zone and the floating-gate electrode. This permits a reduction in the cell size and to higher integration densities. Preferably the floating gate electrodes of at least two cells extend into a single trench.

Claims

1. In a non-volatile memory cell array including a plurality of non-volatile memory cells which are formed at a surface of a semiconductor substrate and which each includes spaced source and drain zones formed in said surface, a trench provided in said surface adjacent the side of said drain zone facing away from the channel zone, a tunnel through dielectric layer disposed on said surface and covering at least the side walls of said trench, and a floating-gate electrode, as the memory electrode, disposed on said dielectric layer and extending into said trench;

the improvement wherein;

said drain zone of at lest two of said non-volatile memory cells are disposed adjacent a single said trench and said floating-gate electrodes of said at lest two memory cells extend into said signal trench so that tunnel current can flow horizontally to the semiconductor surface between a respective said drain zone and the associated one of said floating-gate-electrodes.

2. A non-volatile memory cell array according to claim 1, wherein said trench is rectangular and wherein a respective portion of a side wall of said single trench is covered by each of said floating-gate electrodes of said at least two memory cells.

3. A non-volatile memory cell array according to claim 2, wherein said trench has a depth of approximately 1.5 μ

m.

4. A non-volatile memory cell array according to claim 1, wherein said floating-gate electrodes of said at least two memory cells are arranged radially around said trench.

5. A non-volatile memory cell array according to claim 2, wherein the two said floating-gate electrodes cover portions of two opposite side walls of said rectangular trench.

6. An array according to claim 1, wherein said trench is deeper than said drain zones.

7. An array according to claim 1, wherein said trench is symmetrically disposed between two identical said drain zones.

8. An array according to claim 1, wherein said semiconductor substrate comprises silicon.

9. An array according to claim 1, wherein said gate electrodes comprise polysilicon.

10. In a non-volatile memory cell array including at least first and second non-volatile memory cells formed on a semiconductor substrate and each including a floating-gate field effect transistor having spaced source and drain zones formed in a surface of said semiconductor substrate and defining a channel zone therebetween, and a floating-gate electrode, which serves as the memory electrode, arranged on a tunnel-through dielectric layer disposed on said surface of said semiconductor substrate;

the improvement wherein;

a single trench is formed in said surface of said semiconductor element adjacent the side of the drain zone which faces away from the respective said channel zone of at least each of said first and second memory cells;

said dielectric layer covers at least the side walls of said trench; and

said floating gate electrode of each of said first and second memory cells extends along said dielectric layer into said trench and over respective portions of said side walls such that tunnel current can flow horizontally to the semiconductor surface between said drain zones and respectively associated said floating-gate electrodes.