Semiconductor integrated circuit device

• US 4,990,992 A
• Filed: 10/05/1988
• Issued: 02/05/1991
• Est. Priority Date: 07/27/1983
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchida, Makio
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/253,673
• Time in Patent Office: 853 Days
• Field of Search: 365/72, 365/104, 365/230.03, 357/40, 357/41, 357/45, 357/59
• US Class Current: 257/211
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken the circuit block formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.

Claims

1. A semiconductor integrated circuit device comprising:

a plurality of word lines extending in a first direction;

a plurality of data lines extending in a second direction which is perpendicular to said first direction;

first means for selecting a word line from said plurality of word lines and which applies a signal to the selected word line;

a second means for selecting a pair of data lines from said plurality of data lines;

sub-word lines extending in said first direction and being substantially parallel to said word lines, and at least two sub-word lines connected to each of said plurality of word lines; and

each of said sub-lines being connected to a plurality of memory cells, each memory cell being connected to one of said data lines and the signal from said first means being supplied to said at least two sub-word lines substantially simultaneously.

2. A semiconductor integrated circuit device according to claim 1, wherein each of said memory cells includes a MISFET with a gate electrode and source and drain regions.

3. A semiconductor integrated circuit device according to claim 2, wherein said gate electrode is connected to one of said sub-word lines and one of said source and drain regions is connected to one of said data lines.

4. A semiconductor integrated circuit device according to claim 3, wherein said gate electrode is integrally formed with one of said sub-word lines.

5. A semiconductor integrated circuit device according to claim 4, wherein said word lines are formed of aluminum.

6. A semiconductor integrated circuit device according to claim 5, wherein said sub-word comprise electrically conductive polycrysalline silicon layers.

7. A semiconductor integrated circuit device according to claim 1, wherein said first means is X-address decoder.

8. A semiconductor integrated circuit device according to claim 7, wherein said second means is Y-address decoder.