Signal processing method and device for digital signal reproduction apparatus

• US 4,991,033 A
• Filed: 09/28/1988
• Issued: 02/05/1991
• Est. Priority Date: 09/30/1987
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Takeshita, Kazuyuki
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/250,117
• Time in Patent Office: 860 Days
• Field of Search: 360/32, 360/51, 360/49
• US Class Current: 360/32
• CPC Class Codes: G11B 15/1875 adaptations for special effects or editing signal processing or indexing therefor G11B27/00
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 2220/90 Tape-like record carriers
• CPC Class Codes: G11B 27/005 Reproducing at a different information rate from the information rate of recording for television signals H04N5/783
• CPC Class Codes: G11B 27/3027 used signal is digitally coded

Abstract

Signal processing method and apparatus are provided for use in a digital signal reproduction apparatus which reproduces data divided into plural channels and recorded in plural tracks in parallel. Time division operation is applied to digital signals of plural channels read out from plural tracks for every associated reproduction head and at intervals of predetermined unit time interval. In each unit time interval, digital signals of n consecutive units (where n is an integer not less than 2) supplied from associated reproduction heads are multiplexed with a multiplexing factor of n. The above described multiplexed signals of n units supplied from an identical reproduction head are stored into identical addresses of m (where m is an integer not less than 2) memories, respectively. Digital signals supplied from every reproduction head are successively stored into a different address in each memory. Signals stored in identical addresses of the above described respective memories are read out simultaneously and then signals of respective addresses are read out successively.

Claims

1. A signal processing device for use in a digital signal reproduction apparatus which reproduces digital signals in a record medium in which plural channels of digital signals are recorded thereon in plural tracks, said digital signals being reproduced by plural reproduction heads associated with said plural tracks, said signal processing device comprising:

address signal generation means for generating a write-in address signal and a read-out address signal;

memory means comprising m (where m is an integer not less than

     2) memories for writing and reading, in response to said write-in address signal and said read-out address signal, digital signals which are read out in parallel from plural tracks of said record medium by said plural reproduction heads, time-divided for every associated reproduction heads, and multiplexed with a multiplexing factor of n (where n is an integer not less than

     2), said memories respectively storing signals supplied from an identical reproduction head in identical addresses, each of said memories storing signals supplied from respective reproduction heads in different addresses.

2. A signal processing device according to claim 1, wherein said address signal generation means generates said write-in address signal on the basis of an identification signal included in signals reproduced by said reproduction head.

3. A signal processing device according to claim 1, wherein said memory means writes signals successively into respective memories in a predetermined address sequence in accordance with the write-in address signal supplied from said address signal generation means, and upon completion of the write-in operation, said memory means reads out signals in the same address sequence in accordance with the read-out address signal.

4. A signal processing device for use in a digital signal reproduction apparatus which reproduces digital signals recorded in a record medium in which plural channels of digital signals are recorded thereon in separate tracks each associated with corresponding one of the plural channels, said digital signals being reproduced by plural rotary reproduction heads associated with said respective channels, said signal processing device comprising:

address signal generation means for generating a first address signal, and second and third address signals related to said first address signal by frequency demultiplication;

data sequence conversion means for applying time-division operation to digital signals of plural channels read out in parallel from plural tracks of said record medium by said plural reproduction heads, for every associated reproduction head, in response to said first address signal, and at intervals of predetermined unit time interval and for multiplexing digital signals of n consecutive units (where n is an integer not less than

     2) supplied from associated reproduction heads with a multiplexing factor of n in each unit time interval;

memory means comprising m (where m is an integer) memories and storing said multiplexed signals of n units supplied from an identical reproduction head respectively in identical addresses of m memories simultaneously in response to said second address signal, signals supplied from every reproduction head being successively stored in a different address in each memory, and upon storing data in all addresses of respective memories said memory means reading simultaneously signals stored in identical addresses of respective memories in accordance with said third address signal and then reading digital signals of respective addresses successively; and

inverse sequence conversion means for applying sequence conversion processing to signals read out from said memory means so as to make them equivalent to input signals of said sequence conversion means and for outputting digital signals separately for signals of every reproduction head.

5. A signal processing device according to claim 4, wherein said address signal generation means generates said second address signal on the basis of an identification signal included in signals reproduced by said reproduction head.

6. A signal processing device according to claim 4, wherein said memory means writes signals successively into respective memories in a predetermined address sequence in accordance with the second address signal supplied from said address signal generation means, and upon completion of the write-in operation, said memory means reads out signals in the same address sequence in accordance with the third address signal.

7. A signal processing device according to claim 6, wherein said inverse sequence conversion means performs processing which is inverse with respect to that performed by said sequence conversion means.

8. A signal processing device for use in a digital signal reproduction apparatus which reproduces digital signals recorded in a record medium in which plural channels of digital signals are recorded thereon in separate tracks each associated with corresponding one of the plural channels, said digital signals being reproduced by plural reproduction heads associated with said respective channels, said signal processing device comprising:

sequence conversion means for applying time-division operation to digital signals of plural channels read out in parallel from plural tracks of said record medium by said plural reproduction heads, for every associated reproduction head and at intervals of predetermined unit time interval and for multiplexing digital signals of n consecutive units (where n is an integer not less than

     2) supplied from associated reproduction heads with a multiplexing factor of n in each unit time interval;

memory means comprising m (where m is an integer not less than

     2) memories;

write-in means for storing said multiplexed signals of n units supplied from an identical reproduction head respectively into identical addresses of m memories and for storing signals supplied from every reproduction head successively into a different address in each memory;

read-out means for reading simultaneously signals stored in identical addresses of respective memories of said memory means and then reading signals of respective addresses successively; and

inverse sequence conversion means for applying sequence conversion processing to digital signals read out from said memory means so as to make them equivalent to input signals of said sequence conversion means and for outputting digital signals separately for signals of every reproduction head.

9. A signal processing device according to claim 8, wherein a write-in address signal to said memory is generated on the basis of an identification signal included in signals reproduced by said reproduction head.

10. A signal processing device according to claim 8, wherein said write-in means writes signals successively into respective memories in a predetermined address sequence in accordance with a write-in address signal, and upon completion of the write-in operation, said read-out means reads out signals in the same address sequence in accordance with a read-out address signal.

11. A signal processing device according to claim 10, wherein said inverse sequence conversion means performs processing which is inverse with respect to that performed by said sequence conversion means.

12. A signal processing method for a digital signal reproduction apparatus which reproduces digital signals recorded in a record medium in which plural channels of digital signals are recorded thereon in separate tracks each associated with corresponding one of the plural channels, said digital signals being reproduced by plural rotary reproduction heads associated with said respective channels, said method comprising:

a first step of applying time-division operation to digital signals of plural channels read out from plural tracks of said record medium by said plural reproduction heads, for every associated reproduction head and at intervals of predetermined unit time interval and of multiplexing digital signals of n consecutive units (where n is an integer) supplied from associated reproduction heads with a multiplexing factor of n in each unit time interval;

a second step of storing said multiplexed signals of n units supplied from an identical reproduction head respectively in identical addresses of m (where m is an integer) memories and of storing digital signals supplied from every reproduction head successively in a different address in each memory;

a third step of reading out simultaneously signals stored in identical addresses of said respective memories and of then reading out signals of respective addresses successively; and

a fourth step of applying sequence conversion processing to digital signals read out from said respective memories so as to make them equivalent to reproduced signals supplied from respective reproduction heads and of outputting digital signals separately for signals of every reproduction head.

13. A signal processing method according to claim 12, wherein said second step comprises a step of generating a write-in signal on the basis of an identification signal included in signals reproduced by said reproduction head.

14. A signal processing method according to claim 12, wherein said respective memories write signals successively into respective memories in a predetermined address sequence in accordance with a write-in address signal, and upon completion of the write-in operation, said respective memories read out signals in the same address sequence in accordance with a read-out address signal.

15. A signal processing method according to claim 12, wherein processing performed at said fourth step is inverse with respect to processing performed at said first step.

16. A signal processing device for use in a digital signal reproduction apparatus which reproduces digital signals in a record medium in which plural channels of digital signals are recorded thereon in plural tracks, said plural channels of digital signals being reproduced by plural reproduction heads associated with said plural tracks, respectively, said signal processing device comprising:

address signal generation means for generating a write-in address signal and a read-out address signal;

multiplexing means for applying time division multiplexing operation to said plural channels of digital signals reproduced by said plural reproduction heads; and

memory means for writing and reading, in response to said write-in address signal and said read-out address signal, the time division multiplexed digital signals applied from said multiplexing means in a manner that the digital signals of different channels are stored in different addresses.

17. A signal processing device according to claim 16, wherein said address signal generation means generates said write-in address signal on the basis of an identification signal included in signals reproduced by said reproduction head.

18. A signal processing device according to claim 16, wherein said memory means writes the digital signals in a predetermined address sequence in accordance with the write-in address signal supplied from said address signal generation means, and after completion of the write-in operation, said memory means reads out signals in the same address sequence in accordance with the read-out address signal.

19. A signal processing device for use in a digital signal reproduction apparatus which reproduces digital signals in a record medium in which plural channels of digital signals are recorded thereon in plural tracks, said plural channels of digital signals being reproduced by plural reproduction heads associated with said plural tracks, respectively, said signal processing device comprising;

address signal generation means for generating a write-in address signal and a read-out address signal;

multiplexing means for applying time division multiplexing operation to said plural channels of digital signals, which are read out in parallel from plural tracks of said record medium by said plural reproduction heads, for every channel of the digital signals with a multiplexing factor of n (wherein n is an interger not less than

     2); and

memory means comprising m (where m is an integer) memories for writing and reading, in response to said write-in address signal and said read-out address signal, the time division multiplexed digital signals applied from said multiplexing means in a manner that the digital signals of the same channel are stored in the same addresses and the digital signals of different channels are stored in different addresses.

20. A signal processing device according to claim 19, wherein said address signal generation means generates said write-in address signal on the basis of an identification signal included in signals reproduced by said reproduction head.

21. A signal processing device according to claim 19, wherein said memory means written the digital signals successively into respective memories in a predetermined address sequence in accordance with the write-in address signal supplied from said address signal generation means, and after completion of the write-in operation, said memory means reads out signals in the same address sequence in accordance with the read-out address signal.