Personal computer bus interface chip with multi-function address relocation pins

• US 4,991,085 A
• Filed: 04/13/1988
• Issued: 02/05/1991
• Est. Priority Date: 04/13/1988
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Pleva, Robert M., Catlin, Robert W.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US07/181,138
• Time in Patent Office: 1,028 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85
• US Class Current: 326/82
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

An integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip. The present interface integrated chip combines (a) command decode circuitry for receiving coded signals from the MCA bus and for generating decoded command signals for peripheral devices, (b) pin control circuitry which controls multi-function pins, (c) bus arbitration control circuitry, (d) POS Programmable Option Select register control circuitry to facilitate adapter identification support, (e) ready logic circuitry to facilitate synchronous ready signal generation, (f) circuitry to facilitate device error reporting, (g) external data buffer control, (h) bus response signal generation circuitry, and (j) circuitry to support memory and I-O relocation. The above combination of functions is provided on a single integrated circuit thereby efficiently utilizing the limited number of I-O pins available on the integrated circuit.

Claims

1. An integrated circuit for use in connecting a peripheral device to a microchannel bus, said microchannel bus including command and status lines, a channel reset line, bus arbitration control lines, including a preempt line, a arbitrate/grant line and four arbitration bus priority level (ARB) lines, address lines, data lines, a refresh line, and a channel ready line, said integrated circuit comprising:

command decode means, coupled to said command and status lines, for generating memory read, memory write, I/O read and I/O write output signals;

a plurality of programmable option select (POS) registers;

register control logic means, coupled to a plurality of said command and status lines, for generating read and write signals for said POS registers;

a plurality of multifunction pins;

a plurality of comparators having first inputs coupled to selected ones of said POS registers, second inputs coupled to a group of pins of a first portion of said multifunction pins, and outputs coupled to a second portion of said multifunction pins; and

pin mode control means, responsive to a pin mode input, for coupling said first portion of said multifunction pins to said second comparator inputs and coupling said comparator outputs to said second portion of multifunction pins in a first mode, for providing a first number of said POS register read and write signals to a first number of said multifunction pins in place of a first member of said comparator outputs in a second mode, and for providing a second number, greater than said first number, of said POS register read and write signals to said multifunction pins in a third mode.

3. The integrated circuit of claim 1 or 2 wherein said pin mode input is tied to one of a fixed low level and a fixed high level for said first and second modes and is tied to said channel reset line for said third mode.

4. The integrated circuit of claim 1 or 2 wherein said pin mode control means includes a multiplexer having inputs coupled to a portion of said POS register read and write lines and a portion of said comparator outputs, said multiplexer having outputs coupled to a portion of said multifunction pins and further comprising pin mode logic coupling said pin mode input to a select input of said multiplexer.

5. The integrated circuit of claim 4 further comprising a tri-state buffer coupling a portion of said POS register read and write lines to a portion of said multifunction pins, said tri-state buffer having an enable input coupled to an output of said pin mode logic.

2. An integrated circuit for use in connecting a peripheral device to a microchannel bus, said microchannel bus including command and status lines, a channel reset line, bus arbitration control lines, including a preempt line, a arbitrate/grant line and four arbitration bus priority level (ARB) lines, address lines, data lines, a refresh line, and a channel ready line, said integrated circuit comprising:

command decode means, coupled to said command and status lines, for generating memory read, memory write, I/O read and I/O write output signals;

a priority level register for storing a priority level of said peripheral device;

bus arbitration control means, coupled to said bus arbitration control lines, for comparing bits on said ARB lines to said priority level in response to a signal on said arbitrate/grant line, for providing a signal on said preempt line in response to a DREQ signal from said peripheral device, for providing a DACK signal to said peripheral device if said priority level has a priority equal to said ARB bits to give said peripheral device control of said microchannel bus, and for generating a SUSPEND output signal when said peripheral device has control of said microchannel bus and a signal is detected on said preempt line from another device coupled to said microchannel bus;

a plurality of programmable option select (POS) registers;

register control logic means, coupled to a plurality of said command and status lines, for generating read and write signal for said POS registers;

a plurality of multifunction pins;

a plurality of comparators having first inputs coupled to selected ones of said POS registers, second inputs coupled to a group of pins of a first portion of said multifunction pins, and outputs coupled to a second portion of said multifunction pins; and

pin mode control means, responsive to a pin mode input, for coupling said first portion of said multifunction pins to said second comparator inputs and coupling said comparator outputs to said second portion of multifunction pins in a first mode, for providing a first number of said POS register read and write signals to a first number of said multifunction pins in place of a first number of said comparator outputs in a second mode, and for providing a second number, greater than said first number, of said POS register read and write signals to said multifunction pins in a third mode.