Alarm system

• US 4,991,123 A
• Filed: 01/06/1989
• Issued: 02/05/1991
• Est. Priority Date: 01/06/1989
• Status: Expired due to Fees

• Current Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Original Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Inventors: Casamassima, Mario D.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/293,999
• Time in Patent Office: 760 Days
• Field of Search: 340/525, 340/577, 340/825.08, 340/825.1, 340/825.11, 364/141, 364/550
• US Class Current: 340/525
• CPC Class Codes: G08B 25/04 using a single signalling line, e.g. in a closed loop
• CPC Class Codes: G08B 25/14 Central alarm receiver or annunciator arrangements

Abstract

The invention is a control system comprising a plurality of sensor units, a plurality of output units, and a central processing unit coupled via a data/address bus. Each peripheral unit, i.e. sensor unit or output unit, includes an EEPROM, the Op-code protocol of which is used to provide all addressing and data protocol necessary to support system communication over the bus.

Claims

1. A control system having a central processing unit coupled via a bus to a series of peripheral devices, the processing unit adapted to receive data from a first group of the peripheral devices, termed sensor units, and responding to the data received therefrom, comprising:

an Electronically Erasable Programmable Read Only Memory (EEPROM) associated with each sensor unit coupled to the bus, the EEPROM having a plurality of memory locations and programmed so as to respond to instructions in the form of binary op-codes sent over the bus from the processing unit to the sensor units;

the EEPROM programmed with zeros in all memory locations except for an identifying code in a section of memory unique to each EEPROM;

means within the processing unit for sending a read instruction to the EEPROMs over the bus; and

means within the processing unit for reading the data placed on the bus by the EEPROMs in response to a read instruction in order to determine which of said sensor units responded to the read instruction.

2. A control system as set forth in claim 1 further comprising:

means at each sensor unit for receiving data from an external source;

means for combining the external data with the identifying code from the associated EEPROM such that the external data is placed on the bus only simultaneously with the reading out of the identifying code of the associated EEPROM; and

means within the processing unit for separating the external information from the identifying code when received over the bus.

3. A control system as set forth in claim 2 further comprising:

a second group of peripheral devices coupled to the bus, termed output units;

the output units each having an EEPROM associated therewith, each EEPROM programmed with zeros in all memory locations except for an identifying code stored in a section of memory unique to each EEPROM;

means within the processing unit for selecting an output unit to respond to an alarm condition at a sensor unit;

means within the processing unit for sending response instructions to the output units in response to the external information received from the sensor units simultaneously with the reading out of the identifying code of the output unit which is to respond to the alarm condition;

a response device associated with each output unit for responding to response instruction from the processing unit; and

means within the output units for enabling the output unit to respond to response instructions from the processing unit only simultaneously with the identifying code of the associated EEPROM being read out of the EEPROM.

4. A control system as set forth in claim 3 wherein the identifying code is a single bit set to 1.

5. A control system as set forth in claim 3 wherein the identifying code is a series of bits set to 1.

6. A control system as set forth in claim 3 wherein the means for combining the external information with the identifying code comprises a comparator having first and second inputs and an output, the first input being coupled to receive the external information, the second input being coupled to receive the identifying code and the output being coupled to the bus.

7. A control system as set forth in claim 6 wherein the second input of the comparator is further coupled to a clock signal comprising a train of clock cycles, each cycle comprising a first level and a second level, the first and second levels selected so as to

(i) prevent the comparator from drawing a current from the bus when the data at the first input of the comparator is in the second state,

(ii) cause the comparator to draw a current from the bus when the data at the first input of the comparator is in the first state and the clock signal is in the first state, and

(iii) when the data at the first input is in the first state and the clock signal is in the second state, cause the comparator to draw a current from the bus, if the external data is in the first state, and prevent the comparator from drawing current from the bus, if the external data is in the second state.

8. A control system as set forth in claim 6 wherein the external information is a single bit indicating ON or OFF condition.

9. A control system as set forth in claim 8 wherein the response instruction is a single bit which instructs the response device to activate if in a first state and instructs the response device to remain inactive if in a second state.

10. A control system as set forth in claim 9 wherein the means for enabling the response device only simultaneously with the reading out of the identifying code of the associated EEPROM comprises an AND gate having first and second inputs and an output, the first input being coupled to receive the data supplied from the associated EEPROM in response to a READ instruction, the second input coupled to receive the response instruction from the processing unit, and the output coupled to activate the response device if both inputs are in the second state.

11. A sensor unit for use in an alarm control system wherein a plurality of sensor units are coupled to a central processing unit via a data bus such that the processing unit may poll each sensor unit to determine its status, comprising:

an EEPROM having a single bit of memory set to a first state and all other memory locations set to a second state, the location of the bit set to the first state being different from every other sensor unit coupled to said control system;

a sensing device having an output which is in a first state when deactivated and in a second state when activated;

circuit means for allowing the EEPROM to be coupled to the bus to receive read instructions from the processing unit;

a comparator having first and second input and an output, the first input coupled to the data output pin of the EEPROM, and the second input coupled to the output of the sensing device;

a diode having an anode coupled to the comparator output and a cathode coupled to the bus such that current flow out of the comparator is inhibited; and

the second input of the comparator further coupled to a clock signal comprising a train of clock cycles, each cycle comprising a first level and a second level, the first and second levels selected so as to

(i) prevent the comparator from drawing a current from the bus when the data at the first input of the comparator is in the second state,

(ii) cause the comparator to draw a current from the bus when the data at the first input of the comparator is in the first state and the clock signal is in the first state, and

(iii) when the data at the first input is in the first state and the clock signal is in the second state, cause the comparator to draw a current from the bus, if the external data is in the first state, and prevent the comparator from drawing current from the bus, if the external data as in the second state.

12. An output unit for use in an alarm control system wherein a plurality of output units are coupled to a central processing unit via a data bus such that the processing unit may selectively activate the output units by issuing a timed pulse on the data bus at a specified time, comprising:

an EEPROM having a single bit memory location set to a first state and all other memory locations set to a second state;

circuit means for coupling the EEPROM to the data bus to receive read instructions and the timed pulse from the processing unit;

a response device having an input, the response device being de-activated when the input is in a first state and activated when in a second state; and

an AND-gate having first and second inputs and an output, the first input coupled to the data-out pin of the EEPROM, the second input coupled to receive the clock pulse from the processing unit and the output coupled to the input of the response device.

13. An alarm system including a central control unit and a plurality of sensor units and including a bus means for intercoupling the central control unit and plurality of sensor units, each of said sensors including a programmable memory means having a plurality of memory locations with at least one memory location of each programmable memory means being set to a first state while all other memory locations other than the at least one set to the first state, being set to a second state, said at least one memory location which are set to the first state being selected such that no two sensor units have corresponding memory locations set to the first state, said central control unit including means for sending a read instruction to the programmable memory means over the bus means, and means for reading the data placed on the bus means from the programmable memory means in response to the read instruction in order to determine which sensor units responded to the read instruction.

14. An alarm system as set forth in claim 13 wherein the means for sending a read instruction includes means for sending a binary op-code, readable by the programmable memory means, over the bus means from the central control unit to the plurality of sensor units.

15. An alarm system as set forth in claim 13 wherein said programmable memory means comprises an electronically erasable programmable read only memory.

16. An alarm system as set forth in claim 13 wherein said first state is a binary "one" state and said second state is a binary "zero" state.

17. An alarm system as set forth in claim 13 wherein only a single bit of memory in each memory mean is set to the first state.

18. An alarm system as set forth in claim 13 wherein each sensor unit further comprises means for receiving data from an external source, means for combining the external data with the data read from the associated memory means before it is placed on the bus means such that the external data does not affect the bus mean when the data read from the associated memory means is in the second state and the external data does affect the bus means when the data read from the associated memory means is in the first state, and means within the central control unit for separating the external information from the data read from the associated memory means when received over the bus means.

19. An alarm system as set forth in claim 18 wherein the means for combining the external information with the identifying code comprises a comparator having first and second inputs and an output, the first input being coupled to receive the external information, the second input being coupled to receive the data from the associated memory means, and the output being coupled to the bus means.

20. An alarm system as set forth in claim 18 further comprising a plurality of output units, the output units each having an EEPROM with multiple memory locations associated therewith, each EEPROM having at least one memory location set to the first state and all memory location other than the at least one set to the first state being set to a second state, the at least one memory location to the first state in one output unit EEPROM being different than the at least one memory location set to the first state in any other output unit EEPROM and sensor unit memory means.

21. An alarm system as set forth in claim 18 wherein;

the second input of the comparator is further coupled to a clock signal comprising a train of clock cycles, each cycle comprising a first level and a second level, the first and second levels selected so as to

(i) prevent the comparator from drawing a current from the bus when the data at the first input of the comparator is in the second state,

(ii) cause the comparator to draw a current from the bus when the data at the first input of the comparator is in the first state and the clock signal is in the first state, and

(iii) when the data at the first input is in the first state and the clock signal is in the second state, cause the comparator to draw a current from the bus, if the external data is in the first state, and prevent the comparator from drawing current from the bus, if the external data as in the second state.

22. An alarm system as set forth in claim 21 wherein said central control unit further comprises means for sending READ instructions over the bus means to the output unit EEPROMs, and mean for reading the data placed on the bus means from the output unit EEPROMs in response to the read instructions.

23. An alarm system as set forth in claim 22 further including means within the central control unit for selecting one or more output units to respond to an alarm condition at a sensor unit, means within the central control unit responsive to the external information received from the sensor units for sending response instructions to the output units simultaneously with the reading out of the identifying code of the output unit which is to be activated, a response device associated with each output unit for responding to response instructions from the central control unit, and means within the output units for enabling the output unit to respond to response instructions from the central control unit only simultaneously with the reading out of the identifying code of the EEPROM associated with that output unit.

24. An alarm system as set forth in claim 23 wherein the external information is a single bit indicating an "on" condition if in a first state and an "off" condition if in a second state.

25. An alarm system as set forth in claim 24 wherein the response instruction is a single bit which instructs the response device to activate if in a first state and instructs the response device to remain inactive if in a second state.

26. An alarm system as set forth in claim 25 wherein the means for enabling the response device only simultaneously with the reading out of the identifying code of the associated EEPROM comprises an AND gate having first and second inputs and an output, the first input being coupled to receive the data supplied from the associated EEPROM in response to a READ instruction, the second input coupled to receive the response instruction from the processing unit, and the output coupled to activate the response device if both units are in the second state.

27. A control system comprising;

a plurality of output devices,

a central processing unit for controlling said output devices,

a bus coupling said output devices and said central processing unit together,

each output device comprising a memory storage device having a plurality of storage locations, at least one of said storage locations in each memory device set to a first state such that each memory storage device has a different at least one storage location set to the first state and all other storage locations set to a second state, said memory storage device having an input for receiving instructions from said bus and an output for outputting data stored in said storage locations,

means within said processing unit for issuing an instruction over said bus to said output devices,

means within said processing unit for issuing a pulse on said data bus, at a specified time, and

means associated with each output device, responsive to the simultaneous occurrence of said pulse on said bus and said memory storage device output being in said first state, for generating an output signal.

28. A control system comprising;

a plurality of sensor devices,

a central processing unit for polling said sensor devices,

a bus coupling said sensor devices and said central processing unit together,

each sensor unit comprising a sensing device having an output which is in a first state when a specified condition is sensed and in a second state when said specified condition is not sensed, each of said sensor units further comprising programmable memory storage means having a plurality of storage locations, at least one of said storage locations set to a first state such that each memory storage means has a different at least one memory location set to said first state and all other memory locations set to a second state,

means within said central processing unit for causing said programmable memory storage means to write data onto said bus, and

means within said central processing unit for determining which sensor unit responded to said instruction by determining which programmable memory storage means output data from said storage location set to said first state.

29. A control system as set forth in claim 28 further comprising;

means associated with each sensor unit for combining the output of said sensing device with the output of the associated memory storage means such that the output of said sensing device is inhibited from affecting the bus at all times except simultaneously with the output from said associated memory storage means of said at least one storage location set to said first state.