Specialized communications processor for layered protocols
First Claim
1. In a communication processor for efficient execution of data processes associated with layered communication protocols, said processor having discrete machine cycles of operation and cooperating with an external memory system containing programs of instructions and data related to said instructions, said data comprising header and frame information for said layered communication protocol processes and said instructions comprising at least instructions of first and second types, instructions of said first type pertaining to the processing of said header and frame information data, said instructions of said second type comprising instructions other than those of said first type, the improvement comprising:
- means coupled to said external memory system for retrieving and decoding said instructions;
special purpose logic circuit means coupled to said retrieving and decoding means and said external memory system for performing processes designated by said instructions of said first type, said special purpose logic circuit means being adapted specifically for performing all operations required by each instruction of said first type in a single said machine cycle of operation of said processor; and
general purpose arithmetic logic circuit means coupled to said retrieving means and said external memory system for cooperating therewith to execute processes designated by retrieved instructions of said second type, said general purpose logic circuit means operating under control of said retrieving means for performing functions designated by individual instructions of said second type processor;
said instructions of said first type and the related operations of said special purpose logic circuit means being characterized further in that execution of each such instruction would have required multiple said machine cycles if performed via said general purpose arithmetic logic circuit means.
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Abstract
A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions. Frame processing functions so handled include CRC (cyclic redundancy check) computations, bit insertion/deletion operations and special character detection operations.
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Citations
18 Claims
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1. In a communication processor for efficient execution of data processes associated with layered communication protocols, said processor having discrete machine cycles of operation and cooperating with an external memory system containing programs of instructions and data related to said instructions, said data comprising header and frame information for said layered communication protocol processes and said instructions comprising at least instructions of first and second types, instructions of said first type pertaining to the processing of said header and frame information data, said instructions of said second type comprising instructions other than those of said first type, the improvement comprising:
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means coupled to said external memory system for retrieving and decoding said instructions; special purpose logic circuit means coupled to said retrieving and decoding means and said external memory system for performing processes designated by said instructions of said first type, said special purpose logic circuit means being adapted specifically for performing all operations required by each instruction of said first type in a single said machine cycle of operation of said processor; and general purpose arithmetic logic circuit means coupled to said retrieving means and said external memory system for cooperating therewith to execute processes designated by retrieved instructions of said second type, said general purpose logic circuit means operating under control of said retrieving means for performing functions designated by individual instructions of said second type processor; said instructions of said first type and the related operations of said special purpose logic circuit means being characterized further in that execution of each such instruction would have required multiple said machine cycles if performed via said general purpose arithmetic logic circuit means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of conducting data processes pertaining to communications in a communication network--said network comprising data processing nodes at each of which data processes pertaining to a plural-layered communication protocol may be performed, said processes requiring processing of header and frame information accompanying message data units in each layer of said layered communication protocol, said header and frame information accompanying and delineating message data units being communicated over said network, said header information comprising discrete first, second and third header information units, said first header information unit comprising a set of bits representing status of a respective set of communication conditions which when active require attention in a predetermined order of priority, said second header information unit comprising address information for determining routing of the accompanying message data unit, and said third header information unit comprising a set of bits representing message variable parameters associated with respective message data units, the bits in said third unit requiring rearrangement for accurate extraction of the associated message unit information, said frame information to be processed in each layer comprising cyclic redundancy check (CRC) characters requiring cyclic redundancy check computation processing and control characters uniquely demarking frame positions, said control characters necessitating that accompanying message data units be subjected to bit insertion and deletion processes in order to ensure unique recognizability of the control characters at receiving nodes of said network whereby message data characters do not conflict with said control characters--, said method comprising:
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processing information in multiple said protocol layers at a single processing center at each node of said network in a parallel processing mode;
each said center having a predetermined machine cycle period of operation;
each said center including a general purpose processing section and a plurality of special purpose processing sections, said sections being capable of operating in parallel during any said machine cycle period;
each special purpose section being designed for performing a complex operation in a single said machine cycle which operation if performed in said general purpose section would require multiple said machine cycles for completion; anddirecting performance of complex processing operations relative to each of said header units as well as said CRC computation and said insertion and deletion processes into selected ones of said special purpose sections, whereby individual header unit processing operations, CRC computations and bit insertion and deletion operations are each performed in a single said machine cycle period. - View Dependent Claims (15, 16, 17, 18)
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Specification