Design of a high speed packet switching node

• US 4,991,172 A
• Filed: 10/28/1988
• Issued: 02/05/1991
• Est. Priority Date: 10/28/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cidon, Israel, Gopal, Inder S.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Hsu, Alpus H.
• Application Number:
  US07/264,402
• Time in Patent Office: 830 Days
• Field of Search: 370/94, 370/60, 370/85, 370/85.7, 370/85.9, 370/85.11, 370/85.12, 370/60.1, 370/67, 370/66, 370/94.1, 370/94.2, 370/95.1
• US Class Current: 370/400
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5612 Ring
• CPC Class Codes: H04L 49/107 using shared medium
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction

Abstract

A method of transmitting high speed (1 Gbits/sec), packetized, integrated voice/data through a communications network. This invention, more specifically, deals with the word by word transmission of packets on a parallel transmission bus.

Claims

1. A method of transmitting variable size packets on a parallel communication bus from a FIFO memory of a source adapter to a FIFO memory of a selected destination adapter, said method for each packet of said packets comprising the steps of:

(a) reading said packet, having at least two words therein, from said FIFO memory of said source adapter onto a bus with one word being transmitted on said bus during only one clock cycle, with all words of said packet being transmitted in consecutive clock cycles, with a link address of said packet appearing in a designated word of said packet that is transmitted on said bus and with only one packet being transmitted on said bus at any time, each of said words being large enough so as to contain a complete address, with only one said source adapter having control of said bus at any time, said one source adapter having control of said bus for the duration of one or more full packets being transmitted on said bus;

(b) identifying a first word and a last word of said packet to identify boundaries of said packet; and

(c) comparing, in one clock cycle, said link address in said designated word of said packet with link addresses in all adapters capable of accessing said bus, and writing words of said packet, from said first word to said last word, in FIFO memories of said all adapters whose link addresses match said link address in said designated word.

2. A method as recited in claim 1, wherein said designated word is said first word of said packet that is transmitted on said bus.

3. A method of switching variable size packets between asynchronous read/write FIFO memories of adapters, each of said adapters having access to a parallel communications bus, said method comprising the steps of:

(a) storing each of said packets into a FIFO memory of said memories of a source adapter of said adapters;

(b) for each source adapter of said adapters, reading packets from a corresponding FIFO memory of said memories onto said bus with one word being transmitted on said bus during only one bus clock cycle, with all words of the packet being transmitted on said bus in consecutive bus cycles, with at least one link address being stored in at least one designated word of said packet and with only one of said packets being transmitted on said bus at any time, each of said words being large enough so as to contain a complete link address, with only one of said adapters having control of said bus at any time, said one adapter having control of said bus for the duration of one or more full packets being transmitted on said bus;

(c) for each packet read on said bus, identifying a first and last word of each packet to identify the boundaries of each packet said first and last words being identified by corresponding flags;

(d) for each of said packets read on said bus, comparing in one bus block cycle a corresponding said link address in a corresponding said designated word of said each packet with link addresses in said adapters; and

(e) for each of said packets read on said bus, writing said each packet in each of said FIFO memories of said adapters where link addresses match said link address in said designated word of said each packet.