Dual processor speech recognition system with dedicated data acquisition bus
First Claim
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1. A real time data acquisition and processing system, comprising:
- resident host processor means (24);
input means (32, 34,
46) for receiving data signals representing data to be processed, said input means including an amplifier (46) for amplifying said data signals, said amplifier having a gain programmable in accordance with gain control signals and a bandwidth programmable in accordance with bandwidth control signals, said input means being coupled to a communication bus means (30,
64) and said gain and bandwidth control signals being provided by said resident host processor means via said communication bus means;
signal processor means (62) for processing the amplified data signals and coupled to said resident host processor means via said communication bus means for exchanging communication signals with said resident host processor means serving as a resident host for said signal processor means; and
data acquisition bus means (38,
72) for forwarding said amplified data signals to said signal processor means independently of said communication bus means.
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Abstract
Voice signals amplified in a programmable gain, programmable bandwidth subsystem are digitized and buffered and the digitized signals are transferred over a dedicated high speed bus to a speech processor, thus relieving the speech processor and its resident host of the overhead of high data rate transfers and permitting a relatively low capacity computer to accomplish voice recognition on a real time basis.
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Citations
9 Claims
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1. A real time data acquisition and processing system, comprising:
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resident host processor means (24); input means (32, 34,
46) for receiving data signals representing data to be processed, said input means including an amplifier (46) for amplifying said data signals, said amplifier having a gain programmable in accordance with gain control signals and a bandwidth programmable in accordance with bandwidth control signals, said input means being coupled to a communication bus means (30,
64) and said gain and bandwidth control signals being provided by said resident host processor means via said communication bus means;signal processor means (62) for processing the amplified data signals and coupled to said resident host processor means via said communication bus means for exchanging communication signals with said resident host processor means serving as a resident host for said signal processor means; and data acquisition bus means (38,
72) for forwarding said amplified data signals to said signal processor means independently of said communication bus means. - View Dependent Claims (2, 3, 4, 5)
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6. A real time data acquisition and processing system, comprising:
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resident host proecessor means (24); input means (32, 34,
46) for receiving data signals;signal processor means (62) for processing said data signals; communication bus means (30,
64) for communicating between said resident host processor means and said signal processor means;data acquisition bus means (38,
72) for forwarding said data signals to said signal processor means independently of said communication bus means, said data acquisition bus means comprising analog to digital (A/D) conversion means (80) for receiving and digitizing a continuous stream of said data signals, buffer storage means (76) for temporarily storing said digitized data signals from said A/D conversion means, a first data acquisition bus portion (72) for transfer of digitized data signals between said buffer storage means and said signal processor means, and intelligent peripheral processor means (70) for controlling data transfer over said first data acquisition bus portion; andmeans (78) coupled in common to said communication bus means (64) and said data acquisition bus means (72) for permitting communication between said resident host processor means and said peripheral processor means.
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7. A real time data acquisition and processing system, comprising:
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resident host processor means (24); input means (32, 34,
46) for receiving data signals;signal processor means (62) for processing said data signals; communication bus means (30,
64) for communicating between said resident host processor means and said signal processor means; anddata acquisition bus means (38,
72) for forwarding said data signals to said signal processor means independently of said communication bus means, said data acquisition bus means comprising analog to digital (A/D) conversion means (80) for receiving and digitizing a continuous stream of said data signals, buffer storage means (76) for temporarily storing said digitized data signals from said A/D conversion means, a first data acquisition bus portion (72) for transfer of digitized data signals between said buffer storage means and said signal processor means, intelligent peripheral processor means (70) for controlling data transfer over said first data acquisition bus portion, and direct memory access (DMA) control means (82) for controlling storage of digitized data signals in said buffer storage means (76) via said first data acquisition bus portion according to a DMA process. - View Dependent Claims (8)
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9. A real time data acquisition and processing system, comprising:
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resident host processor means (24); input means (32, 34,
46) for receiving data signals representing data;signal processor means (62) for processing said data signals; communication bus means (30,
64) for communication between said resident host processor means and said signal processor means;data acquisition bus means (38,
72) for forwarding said data signals to said signal processor means independently of said communication bus means;intelligent peripheral processor means (70) for controlling data transfer over at least a portion (72) of said data acquisition bus means; and host attachment means (42) coupled to said communication bus means (64), said data acquisition bus means (72) and said signal processor means (62), for selectively connecting said signal processor means to either said communication bus means whereby said resident host processor means operates as a local host for said signal processor means, or to said data acquisition bus means whereby said peripheral processor means operates as a local host for said signal processor means.
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Specification