Trench gate structure with thick bottom oxide

• US 4,992,390 A
• Filed: 07/06/1989
• Issued: 02/12/1991
• Est. Priority Date: 07/06/1989
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Chang, Hsueh-Rong
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, D.
• Application Number:
  US07/376,072
• Time in Patent Office: 586 Days
• Field of Search: 437/41, 437/42, 437/38, 437/67, 357/23.4
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Improved trench gate field effect devices are provided by forming a thick oxide at the bottom of the trench. This thick oxide may be preferably formed by ion implantation into the bottom of the trench.

Claims

1. A method of fabricating a trench gate semiconductor device comprising the steps of:

(a) providing a silicon semiconductor wafer of a first type conductivity;

(b) growing a thermal oxide layer on a first major surface of said wafer;

(c) depositing a thin silicon nitride layer on said thermal oxide layer;

(d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon;

(e) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location;

(f) reactive ion etching a trench into said silicon material;

(g) implanting oxygen ions into the bottom wall of said trench;

(h) thermal annealing said second conductivity type implanted region and said oxygen implanted region, respectively, to form the desired second conductivity type region and silicon oxide;

(i) removing damaged material from the sidewalls of said trench and any silicon on the bottom of said trench over said silicon oxide;

(j) growing a thin gate oxide layer on the sidewalls of said trench;

(k) filling said trench with conductive gate material;

(l) planarizing said wafer by removing said conductive gate material from over said reactive ion etching mask;

(m) removing said reactive ion etching mask;

(n) forming a first conductivity type region in said second conductivity type region adjacent said first major surface of said wafer; and

(o) forming metallic electrodes on said device.

2. The method recited in claim 1 wherein step (e) comprises the steps of:

(1) depositing a thick silicon oxide layer over said silicon nitride layer;

(2) providing a patterned mask over said thick oxide layer; and

(3) reactive ion etching a trench in said thick oxide layer in the opening in said mask.

3. A method of fabricating a trench gate semiconductor device comprising the steps of:

(a) providing a silicon semiconductor wafer of a first type conductivity;

(b) growing a thermal oxide layer on a first major surface of said wafer;

(c) depositing a thin silicon nitride layer over said thermal oxide layer;

(d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon of said wafer;

(e) annealing said implanted dopant to form a desired second conductivity type region;

(f) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location;

(g) reactive ion etching a trench into said silicon material;

(h) removing damaged surface material from the walls of said trench;

(i) growing a thin gate oxide on the walls of said trench;

(j) forming a protective layer on the sidewalls of said trench;

(k) growing a thick oxide layer at the bottom of said trench;

(l) removing said protective layer from said sidewalls;

(m) filling said trench with conductive gate material;

(n) planarizing said wafer to expose said reactive ion etching masking layer;

(o) removing said reactive ion etching mask;

(p) forming a first conductivity source region in said second conductivity type region adjacent said first major surface of said wafer; and

(q) forming metallic electrodes on said device.

4. The method recited in claim 3 wherein step (f) comprises the steps of:

(1) depositing a thick silicon oxide layer over said silicon nitride layer;

(2) providing a patterned photoresist layer over said thick oxide layer; and

(3) reactive ion etching a trench in said thick oxide layer.

5. The method recited in claim 4 wherein step (j) comprises:

depositing a silicon nitride layer on said wafer; and

removing said silicon nitride layer from the bottom of said trench.