Transistor circuit

• US 4,992,755 A
• Filed: 01/19/1990
• Issued: 02/12/1991
• Est. Priority Date: 01/17/1989
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Dikken, Jan, Schumacher, Hans-Jurgen, Seevinck, Evert
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/467,340
• Time in Patent Office: 389 Days
• Field of Search: 330/253, 330/257, 330/258, 330/259, 307/475
• US Class Current: 330/253
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45654 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A transistor circuit comprising a first differential amplifier which is composed of a differential pair and a current mirror. The transistor circuit further comprises a second differential amplifier which measures a differential offset voltage in the first differential amplifier and reduces this offset voltage by means of common mode current feedback. The transistor circuit thus provides a stable amplifier having a high speed and a low offset voltage which can be used advantageously in a logic output buffer so that, for example, an ECL output buffer can be realized in CMOS.

Claims

1. A transistor circuit comprising a first and a second transistor connected as a first differential amplifier and coupled to a common node via a common electrode, a current mirror having an input network connected to a main channel of the first transistor via a first output terminal, an output network of said current mirror being connected to a main channel of the second transistor via a second output terminal, a second differential amplifier having a first and second input coupled to the first and the second output terminal, respectively, an output of said second differential amplifier being coupled to controllable current conductor means for the common mode supply of current to and the common mode draining of current from the first and the second output terminal.

2. A transistor circuit as claimed in claim 1, wherein a first response time of a signal variation on the first and the second output terminal in reaction to an input signal variation of the first differential amplifier is shorter than a second response time of a signal variation on the output of the second differential amplifier in reaction to a signal variation on the first and the second output terminal.

3. A transistor circuit as claimed in claim 2, wherein the controllable current conductor means are coupled to the first and to the second output terminal.

4. A transistor circuit as claimed in claim 3, wherein the controllable current conductor means comprise a third and a fourth transistor having control electrodes connected to the output of the second differential amplifier, means connecting a channel of the third and the fourth transistor between the first and second output terminal, respectively, and a power supply terminal.

5. A transistor circuit as claimed in claim 2, wherein the second differential amplifier comprises a third and a fourth transistor connected as a differential amplifier and coupled, by way of respective control electrodes, to the first and the second output terminals, respectively, a main channel of the third transistor including an input network of a further current mirror, an output network of which is connected in a main channel of the fourth transistor via the output of the second differential amplifier.

6. A transistor circuit as claimed in claim 1 wherein the controllable current conductor means are coupled to the first and to the second output terminal.

7. A transistor circuit as claimed in claim 6, wherein the controllable current conductor means comprise a third and a fourth transistors having control electrodes connected to the output of the second differential amplifier, means connecting a channel of the third and the fourth transistor between the first and second output terminal, respectively, and a power supply terminal.

8. A transistor circuit as claimed in claim 7 wherein said control electrodes are also coupled to a power supply terminal via a capacitive element.

9. A transistor circuit as claimed in claim 6 wherein the controllable current conductor means are coupled to the common node.

10. A transistor circuit as claimed in claim 9, wherein the controllable current conductor means comprise a third transistor having a control electrode connected to the output of the second differential amplifier, a channel of the third transistor being connected between the common node and a power supply terminal.

11. A transistor circuit as claimed in claim 1 wherein the second differential amplifier comprises a third and fourth transistor connected as a differential amplifier and which are coupled, by way of respective control electrodes, to the first and second output terminal, respectively, a main channel of the third transistor including an input network of a further current mirror, an output network of which is included in a main channel of the fourth transistor via the output of the second differential amplifier.

12. A transistor circuit as claimed in claim 11, wherein the third and the fourth transistor are of n-type conductivity.

13. A transistor circuit as claimed in claim 1 further comprising a resistor coupled between the first and the second output terminal.

14. A logic output buffer comprising a transistor circuit as claimed in claim 1.

15. A transistor circuit as claimed in claim 1, wherein the controllable current conductor means are coupled to the common node.

16. A transistor circuit as claimed in claim 15, wherein the controllable current conductor means comprise a third transistor having a control electrode connected to the output of the second differential amplifier, a channel of the third transistor being connected between the common node and a power supply terminal.

17. A transistor circuit as claimed in claim 16 wherein said control electrode is also coupled to a power supply terminal via a capacitive element.

18. A transistor circuit as claimed in claim 1 wherein the common node is connected directly to a power supply terminal.

19. A transistor circuit comprising:

first and second transistors connected as a first differential amplifier with a main electrode of each transistor connected in common to a circuit node,

a current mirror having an input branch and an output branch connected in first and second series circuits with said first and second transistors, respectively,

a second differential amplifier having first and second inputs coupled to first and second output terminals, respectively, of the first differential amplifier,

a controllable current conductor means for the common mode supply of current to and the common mode draining of current from the first and the second output terminals of the first differential amplifier, and

means coupling an output of said second differential amplifier to said controllable current conductor means in a manner so as to reduce an offset voltage, if present, at said output terminals of the first differential amplifier.

20. A transistor circuit as claimed in claim 19 further comprising a feedback circuit coupling at least one of said output terminals of the first differential amplifier to a control electrode of one of said first and second transistors of the first differential amplifier.

21. A transistor circuit as claimed in claim 20 wherein the feedback circuit includes a third transistor and said first and second transistors comprise MOS field effect transistors of one polarity and said current mirror comprises fourth and fifth MOS field effect transistors of opposite polarity to that of said first and second transistors and connected in said input branch and said output branch, respectively.

22. A transistor circuit as claimed in claim 20 further comprising a signal input terminal coupled to a control electrode of the other one of said first and second transistors.

23. A transistor circuit as claimed in claim 20 further comprising a resistor coupled between the first and second output terminals of the first differential amplifier.

24. A transistor circuit as claimed in claim 19 further comprising a capacitor coupled to said output of the second differential amplifier and to said circuit node of the first differential amplifier thereby to delay the response of the second differential amplifier relative to that of the first differential amplifier.

25. A transistor circuit as claimed in claim 19 wherein said controllable current conductor means comprise third and fourth transistors coupled between said first and second output terminals of the first differential amplifier and said circuit node, and wherein said coupling means connects the output of the second differential amplifier to control electrodes of the third and fourth transistors.

26. A transistor circuit as claimed in claim 19 wherein said controllable current conductor means comprise a third transistor coupled between said circuit node and a power supply terminal of the transistor circuit, and wherein said coupling means connects the output of the second differential amplifier to a control electrode of the third transistor.

27. A transistor circuit as claimed in claim 19 wherein the second differential amplifier comprises third and fourth transistors, said transistor circuit further comprising a second current mirror having an input branch and an output branch connected in third and fourth series circuits with said third and fourth transistors, respectively.

28. A transistor circuit as claimed in claim 27, wherein the third and the fourth transistor are of n-type conductivity.

29. A transistor circuit as claimed in claim 19 wherein said first and second series circuits are connected in parallel between first and second terminals of a source of DC supply voltage, and further comprising a capacitor coupled to said output of the second differential amplifier and to one of said first and second terminals of the DC supply voltage.