Digital phase-locked loop biphase demodulating method and apparatus
First Claim
1. A method for decoding digitally-encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring midway through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising the steps of:
- sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency;
detecting whether or not a transition of the transmission signal occurred within said sample and successively storing with respect to time binary representations of whether or not a transition occurred within said sample;
generating a clock signal with a digital phase-locked loop which can be either advanced or retarded in phase in response to a phase-error signal and a phase-error direction indicator;
maintaining a known and constant phase relationship between the phase-locked loop clock and the received clock of the transmission signal by periodically testing the stored transition representations and generating a phase-error signal and direction indicator when a phase error between the phase-locked loop clock and the received clock signal exists and then using the phase-error signal and direction indicator to advance or retard the phase-locked loop clock accordingly; and
using the phase-locked loop clock to decode a stored transition representation as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of the input bit cycle, wherein a transition occurring before a time interval containing the 3/4-bit time as measured by the phase-locked loop clock is decoded as a mid-bit transition while a transition occurring after a time interval containing the 3/4-bit time is decoded as the start of a new bit cycle.
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Abstract
A method and apparatus for demodulating biphase-encoded signals is disclosed. A digital phase-locked loop produces a clock signal which is in phase with the clock signal of the biphase-encoded input signal. The clock signal from the phase-locked loop is then used to derive the data signal from the biphase-encoded input signal in a manner which enhances tolerance to edge skewing.
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Citations
12 Claims
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1. A method for decoding digitally-encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring midway through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising the steps of:
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sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample and successively storing with respect to time binary representations of whether or not a transition occurred within said sample; generating a clock signal with a digital phase-locked loop which can be either advanced or retarded in phase in response to a phase-error signal and a phase-error direction indicator; maintaining a known and constant phase relationship between the phase-locked loop clock and the received clock of the transmission signal by periodically testing the stored transition representations and generating a phase-error signal and direction indicator when a phase error between the phase-locked loop clock and the received clock signal exists and then using the phase-error signal and direction indicator to advance or retard the phase-locked loop clock accordingly; and using the phase-locked loop clock to decode a stored transition representation as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of the input bit cycle, wherein a transition occurring before a time interval containing the 3/4-bit time as measured by the phase-locked loop clock is decoded as a mid-bit transition while a transition occurring after a time interval containing the 3/4-bit time is decoded as the start of a new bit cycle. - View Dependent Claims (2, 3)
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4. An apparatus for decoding digitally-encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring midway through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising:
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means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample and successively storing binary representations of whether or not a transition occurred within said sample in a shift register; means for generating a clock signal with a digital phase-locked loop which can be either advanced or retarded in phase in response to a phase-error signal and a phase-error direction indicator; means for ascertaining whether a known and constant phase relationship between the phase-locked loop clock and the received clock of the transmission signal exists by periodically testing the transition representations stored in said shift register and generating a phase-error signal and direction indicator when a phase error between the phase-locked loop clock and the received clock signals is present; means for advancing or retarding the phase-locked loop clock according to the phase-error signal and direction indicator to maintain a known and constant phase relationship between the phase-locked loop clock and the received clock; and means for using the phase-locked loop clock to decode a transition representation stored in said shift register as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of the input bit cycle wherein a transition occurring before a time interval containing the 3/4-bit time as measured by the phase-locked loop clock is decoded as a mid-bit transition while a transition occurring after a time interval containing the 3/4-bit time is decoded as the start of a new bit cycle. - View Dependent Claims (9, 10)
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5. A method for decoding digitally-encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle with a one during the second half of the bit cycle represents a data signal of one polarity, and a one during the first half of the bit cycle with a zero during the second half represents a data signal of the opposite polarity, comprising the steps of:
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sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample and successively storing with respect to time binary representations of whether or not a transition occurred; generating a clock signal with a digital phase-locked loop which can be either advanced or retarded in phase in response to a phase-error signal and a phase-error direction indicator; maintaining a known and constant phase relationship between the phase-locked loop clock and the received clock of the transmission signal by periodically testing the stored transition representations and generating a phase-error signal and direction indicator when a phase error between the phase-locked loop clock and the received clock signals exist and then using the phase-error signal and direction indicator to advance or retard the phase-locked loop clock accordingly; and using the phase-locked loop clock to decode a stored transition representation as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of the input bit cycle wherein a transition occurring before a time interval containing the 3/4-bit time as measured by the phase locked loop clock is decoded as a mid-bit transition while a transition occurring after a time interval containing the 3/4-bit time is decoded as the start of a new bit cycle. - View Dependent Claims (6, 7)
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8. An apparatus for decoding digitally-encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle with a one during the second half of the bit cycle represents a data signal of one polarity, and a one during the first half of the bit cycle with a zero during the second half represents a data signal of the opposite polarity, comprising:
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means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample and successively storing binary representations of whether or not a transition occurred within said sample in a shift register; means for generating a clock signal with a digital phase-locked loop which can be either advanced or retarded in phase in response to a phase-error signal and a phase-error direction indicator; means for ascertaining whether a known and constant phase relationship between the phase-locked loop clock and the received clock of the transmission signal exists by periodically testing the transmission representations stored in said shift register and generating a phase-error signal and direction indicator when a phase error between the phase-locked loop clock and the received clock signals is present; means for advancing or retarding the phase-locked loop clock according to the phase-error signal and direction indicator to maintain a known and constant phase relationship between the phase-locked loop clock and the received clock; and means for using the phase-locked loop clock to decode a transition representation stored in said shift register as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of the input bit cycle wherein a transition occurring before a time interval containing the 3/4-bit time as measured by the phase-locked loop clock is decoded as a mid-bit transition while a transition occurring after a time interval containing the 3/4-bit time is decoded as the start of a new bit cycle. - View Dependent Claims (11, 12)
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Specification