Microcomputer having a program mode setting circuit

• US 4,992,937 A
• Filed: 03/22/1990
• Issued: 02/12/1991
• Est. Priority Date: 01/18/1985
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hemmi, Toru
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/501,332
• Time in Patent Office: 327 Days
• Field of Search: 364/200, 364/900
• US Class Current: 713/100
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence

Abstract

A microcomputer comprises at least one external terminal through which a plurality of pulse signals, each of which as different pulse widths, are received, a pulse width measuring circuit measuring a pulse width of a received pulse signal, and an address generating circuit generating a plurality of addresses, a selecting circuit selecting one of the plurality of addresses. The microcomputer executes a program designated by the selected address.

Claims

1. A microcomputer comprising a program memory storing a plurality of instructions for a program, a program counter for accessing said program memory to read an instruction from an address location of said program memory designated by address information of said program counter, a central processing unit executing the instruction read from said program memory, a reset terminal supplied with a reset pulse signal made of a variable width of single pulse, an initialization circuit coupled to said reset terminal and said central processing unit and initializing said central processing unit in response to said reset pulse signal, a pulse width measuring circuit having an input node coupled to said reset terminal and a plurality of output nodes provided in correspondence with different pulse widths of said reset signal, said pulse width measuring circuit measuring the pulse width of said reset pulse signal and producing a selection signal at one of said output nodes in response to the measured pulse width of said reset pulse signal, and an address generating circuit storing a plurality of program start addresses and coupled between each of said output nodes of said pulse width measuring circuit and said program counter, said address generating circuit selectively applying one of said program start addresses to said program counter in response to said selection signal produced at said one of said output nodes, whereby said central processing unit is initialized by the received reset pulse signal and thereafter starts to execute the instructions stored in said program memory from an instruction that is stored in an address location of said program memory designated by the program start address which is applied to said program counter in accordance with the pulse width of said received reset pulse signal.

2. The microcomputer as claimed in claim 1, wherein said pulse width measuring circuit includes means for generating a train of clock pulses, means for counting said clock pulses during a time period corresponding to the pulse width of said reset pulse signal and means for decoding a count value of said counting means to produce said selection signal at said one of said output nodes.

3. The microcomputer as claimed in claim 1, wherein said address generating circuit includes a plurality of registers each one of said registers storing each one of said program addresses and connected to one of said output terminals of said pulse width measuring circuit, such that when an output signal is produced on one of said plurality of output terminals, a respective one of said plurality of registers will read-out its program start address and means for transferring the read-out program start address to said program counter.

4. A microcomputer comprising a memory storing a plurality of programs, a program counter coupled to said memory for accessing said memory to read a program therefrom by use of address information of said program counter, a central processing unit executing the program read from said memory, an external terminal for receiving a control pulse signal made of a variable width of a single pulse, means coupled to said external terminal for detecting the pulse width of said control pulse signal to produce a detection signal representative of the pulse width of said control pulse signal, storing means provided independently of said memory for storing a plurality of program start addresses, means coupled to said detecting means and said storing means for outputting one of said program start addresses from said storing means in response to said detection signal, and means for applying said one of said program start addresses read from said storing means to said program counter, whereby said central processing unit stops executing one of said programs by the application of said control pulse signal and thereafter starts to execute another one of said programs in response to the program start address which is applied to said program counter determined in accordance with the pulse width of said control pulse signal.

5. The microcomputer as claimed in claim 4, wherein said external terminal is a reset terminal and said control pulse signal is a reset signal and said central processing unit is initialized by the application of said reset signal and thereafter starts to execute said other one of said programs.

6. The microcomputer as claimed in claim 4, wherein said external terminal is an interrupt terminal and said control pulse signal is an interrupt request signal and said central processing unit suspends temporarily executing said one of said programs and thereafter starts to execute said other one of said programs.

7. A microcomputer comprising:

a program execution unit, a program memory storing a plurality of programs with program start addresses, each of said programs operating said program execution unit, first means for receiving any one of a plurality of external pulse signals which have different pulse widths, each of said pulse widths of said external pulse signals corresponding to a respective one of said program start addresses, second means coupled to said first means for measuring a pulse width of the received external pulse signal, third means for designating one of said program start addresses of said program memory in accordance with the measured pulse width of said received external pulse signal, and fourth means coupled to said first means and said program execution unit for operatively initializing said program execution unit at a predetermined state in response to application of any one of said external pulse signals to said first means, whereby the external pulse signal received by said reset terminal initializes said program execution unit and designates one of the program start addresses corresponding to the pulse width of the received external pulse signal.

8. A microcomputer as claimed in claim 7 wherein said second means comprises:

a sampling signal generator means for generating a plurality of sequential sampling pulses;

gate means having a first input terminal connected to receive said sequential sampling pulses, a second input terminal connected to said reset terminal and an output terminal, said gate means passing said sequential sampling pulses at said output terminal during a time when the external pulse signal is received by said reset terminal; and

counter means for counting the number of sequential sampling pulses passed by said gate means, and producing an output count indicative of the width of said external pulse signal received.

9. A microcomputer as claimed in claim 8, wherein said gate means is a two-input AND gate.

10. A microcomputer as claimed in claim 7, wherein said third means comprises:

decoder means connected to receive the output count from said second means and having a plurality of output terminals each corresponding to each of the pulse widths of said external pulse signals, said decoder means selectively actuating one of said plurality of output terminals; and

a plurality of program start address registers, a respective one of said registers each being connected to a respective one of said output terminals of said decoder means, such that when an output signal is produced on one of said plurality of output terminals, a respective one of said registers will output its predetermined start address.

11. A microcomputer comprising:

a program execution unit, a program memory storing a plurality of programs with program start addresses, each of said programs operating said program execution unit, a first means for receiving an external pulse signal of a variable width of a single pulse, a pulse width measuring circuit coupled to said first means for measuring the pulse width of the external pulse signal received by said first means, said pulse width measuring circuit producing an output signal indicative of said measured pulse width of the received external pulse signal, an address generating circuit connected to said pulse width measuring circuit and said program memory for designating one of said program start addresses in accordance with the output signal produced by said pulse width measuring circuit, and an initialization circuit coupled to said first means and said program execution unit for initializing said program execution unit for initializing said program execution unit at a predetermined state in response to the receipt of said external pulse signal to said first means, whereby said program execution unit is initialized in response to the received external pulse signal and one of said program start addresses is designated in accordance with the measured pulse width of said received external pulse signal.

12. A microcomputer as claimed in claim 11, wherein said pulse width measuring circuit comprises:

a sampling signal generator means for generating a plurality of sequential sampling pulses;

gate means having a first input terminal connected to receive said sequential sampling pulses, a second input terminal coupled to said reset terminal means and an output terminal, said gate means operatively passing said sequential sampling pulses at said output terminal wherein the external pulse signal is being received; and

counter means for counting the number of sequential sampling pulses passed by said gate means, and producing an output count indicative of the width of said external pulse signal received.

13. A microcomputer as claimed in claim 12, wherein said gate means is a two-input AND gate,

14. A microcomputer as claimed in claim 11, wherein said

pulse width measuring circuit includes a counter for operatively performing a counting operation, control means for enabling said counter in response to the received external pulse signal, and decoder means coupled to receive the output signal from said counter and having a plurality of output terminals provided in correspondence with different pulse widths of said external pulse signals, said decoder means selectively activating one of said plurality of output terminals in accordance with the measured pulse width of the received external pulse signal;

and said address generating circuit includes;

a plurality of program start address registers, a respective one of said registers being connected to a respective one of said output terminals of said decoder means, such that when an output signal is produced on one of said plurality of output terminals, a respective one of said registers will designate its program start address.

15. A microcomputer comprising:

a program execution unit, a program memory storing a plurality of programs with program start addresses, each of said programs operating said program execution unit, an external terminal for receiving any one of a plurality of single pulse type interrupt signals which have different pulse widths, interrupt control circuit means coupled to said external terminal and said program execution unit, said interrupt control circuit means interrupting an operation performed by said program executing unit each time an interrupt signal is received at said external terminal, pulse width measuring means coupled to said external terminal for measuring a pulse width of the interrupt signal received by said external terminal, and address generating means coupled to said pulse width measuring means and said program memory for designating one of said program start addresses of said program memory in correspondence with the pulse width of the received interrupt signal measured by said pulse width measuring means, whereby the operation of said program execution unit is interrupted in response to the received interrupt signal and one of the program start addresses of said program memory is designated in accordance with the pulse width of said received interrupt signal.